• Korean Chemical Engineering Research
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• v.55 no.2
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• pp.275-278
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• 2017

Heterogeneous semiconductor composites have been widely used to establish high-performance microelectronic or optoelectronic devices. During a deposition of silicon atoms on silicon/germanium compound surfaces, germanium (Ge) atoms are segregated from the substrate to the surface and are mixed in incoming a silicon layer. To suppress Ge segregation to obtain the interface sharpness between silicon layers and silicon/germanium composite layers, approaches have used silicon hydride gas species. The hydrogen atoms can play a role of inhibitors of silicon/germanium exchange. However, there are few kinetic models to explain the hydrogen effects. We propose using segregation probability which is affected by hydrogen atoms covering substrate surfaces. We derived the model to predict the segregation probability as well as the profile of Ge fraction through layers by using chemical reactions during silicon deposition.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.39-45
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• 2016

In this paper, prcess modeling of germanium condensation has been performed and a germanium PMOSFET having nanowire channel implented by the condensation process has been designed and characterized by device simulations. Based on the previous experimental results, our modeling results demonstrate that the ratio of germanium concentration at the silicon germanium-silicon dioxide interface ($C_S$) to that in the bulk region ($C_B$) which are obtainable during the germanium condensation is approximately 4.03 and the effective diffusion coefficient ($D_{eff}$) of germanium atom is $3.16nm^2/s$. Furthermore, a germanium nanowire-channel PMOSFET having the ultra-thin germanium channel on the silicon core that can be fabricated by the germanium condensation has been designed and characterized. As the result, it is confirmed that the proposed device having the coaxial nanowire consisting of silicon core and germanium channel might have superior performances over the device with either all-silicon or all-germanium channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Journal of the Korean Vacuum Society
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• v.20 no.2
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• pp.77-85
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• 2011

The silicon-germanium (SiGe) alloy, which is compatible with silicon semiconductor technology and has a smaller band gap and a lower thermal conductivity than silicon, has been used to fabricate electronic devices such as transistors, photodetectors, solar cells, and thermoelectric devices. This paper reviews the application of SiGe alloys to electronic devices and related technical issues. Since the SiGe alloy comprises germanium whose band gap is smaller than silicon, its band gap is also smaller than that of silicon irrespective of the ratio of silicon to germanium. This narrow band gap of SiGe enables the base thickness of bipolar transistors to decrease without a loss in current gain so that it is possible to improve the speed of bipolar transistors by adopting the SiGe-base. In addition, the conversion efficiency of solar cells is enhanced by the absorption of long-wavelength light in the SiGe absorption layer. Phonon scattering caused by the irregular distribution of alloying elements induces the lower thermal conductivity of SiGe than those of pure silicon and germanium. Because a thin film layer with a low thermal conductivity suppresses thermal conduction through a thermal sink, the SiGe alloy is considered to be a promising material for silicon-based thermoelectric systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• Current Photovoltaic Research
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• v.8 no.3
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• pp.94-101
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• 2020

This study was trying to focus on achieving high efficiency of multi junction solar cell with thin film silicon solar cells. The proposed thin film Si-Ge/c-Si tandem junction solar cell concept with a combination of low-cost thin-film silicon solar cell technology and high-efficiency c-Si cells in a monolithically stacked configuration. The tandem junction solar cells using amorphous silicon germanium (a-SiGe:H) as an absorption layer of upper sub-cell were simulated through ASA (Advanced Semiconductor Analysis) simulator for acquiring the optimum structure. Graded Ge composition - effect of E_g profiling and inserted buffer layer between absorption layer and doped layer showed the improved current density (J_sc) and conversion efficiency (η). 13.11% conversion efficiency of the tandem junction solar cell was observed, which is a result of showing the possibility of thin film Si-Ge/c-Si tandem junction solar cell.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.11a
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• pp.75-75
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• 1999

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.7
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• pp.653-657
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• 2015

A numerical investigation to simulate the selective growth of silicon-germanium quantum-dots via local surface diffusivity enhancement is presented. A nonlinear equation for the waviness evolution of film surface is derived to consider the effects of spatially-varying diffusivity, influenced by a surface temperature profile. Results show that the morphology of the initially planar film shapes into an undulated surface upon perturbation, and a steady-state solution describes a fully grown quantum-dot. The present study points toward a fabrication technique that can obtain selectivity for self-assembly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.