• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.30-34
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• 2019

We analyzed how the features in plasma information based virtual metrology (PI-VM) for SiO₂ etching depth with variation of 5% contribute to the prediction accuracy, which is previously developed by Jang. As a single feature, the explanatory power to the process results is in the order of plasma information about electron energy distribution function (PI_EEDF), equipment, and optical emission spectroscopy (OES) features. In the procedure of stepwise variable selection (SVS), OES features are selected after PI_EEDF. Informative vector for developed PI-VM also shows relatively high correlation between OES features and etching depth. This is because the reaction rate of each chemical species that governs the etching depth can be sensitively monitored when OES features are used with PI_EEDF. Securing PI_EEDF is important for the development of virtual metrology (VM) for prediction of process results. The role of PI_EEDF as an independent feature and the ability to monitor variation of plasma thermal state can make other features in the procedure of SVS more sensitive to the process results. It is expected that fault detection and classification (FDC) can be effectively developed by using the PI-VM.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.106-112
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• 1990

The progress of oxidation of a porous silicon layer(PSL) was studied by examining the temperature dependence of the oxidation and the infrared absorption spectra. Thick OPSL(oxidized porous silicon layer). which has the same properties as thermal $SiO_{2}$ of bulk silicon, is formed in a short time by two steps wet oxidation of PSL at $700^{\circ}C$, 1 hr and $1100^{\circ}C$, 1 hr. Etching rate, breakdown strength of the OPSL are strongly dependent on the oxidation temperature, oxidation atmosphere. And its breakdown field was ${1\MV/cm^-2}$ MV/cm The oxide film stress was determined through curvature measurement using a dial gauge. During oxidation at temperature above $1000^{\circ}C$ in dry $O_{2}$, stress on the order of ${10^9}\dyne/{cm^2}{-10^10}\dyne/{cm^2}$ are generated in the OPSL.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3310-3312
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• 1999

We have studied the method of silicon direct bonding using the mixture of $HNO_$, $H_2O_2$, and HF chemicals called the controlled slight etch (CSE) solution for the effective wafer cleaning. CSE, two combinations of oxidizing and etching agents, have been used to clean the silicon surfaces prior to wafer bonding. Two wafers of silicon and silicon dioxide were contacted each other at room temperature and postannealed at $300{\sim}1100^{\circ}C$ in $N_2$ ambient for 2.5 h. We have cleaned silicon wafers with the various HF concentrations and characterized the parameters with regard to surface roughness, chemical nature, chemical oxide thickness, and bonding energy. It was observed that the chemical oxide thickness on silicon wafer decreased with increasing HF concentrations. The initial interfacial energy and final energy postannealed at $1100^{\circ}C$ for 2.5h measured by the crack propagation method was 122 $mJ/m^2$ and 2.96 $mJ/m^2$, respectively.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.32-35
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• 2013

In this paper, a manufacturing process was developed for fabricating high-quality AlGaN/GaN high electron mobility transistors (HEMTs) on silicon carbide (SiC) substrates. Various conditions and processing methods regarding the ohmic contact and pre-metal-deposition $BCl_3$ etching processes were evaluated in terms of the device performance. In order to obtain a good ohmic contact performance, we tested a Ti/Al/Ta/Au ohmic contact metallization scheme under different rapid thermal annealing (RTA) temperature and time. A $BCl_3$-based reactive-ion etching (RIE) method was performed before the ohmic metallization, since this approach was shown to produce a better ohmic contact compared to the as-fabricated HEMTs. A HEMT with a 0.5 ${\mu}m$ gate length was fabricated using this novel manufacturing process, which exhibits a maximum drain current density of 720 mA/mm and a peak transconductance of 235 mS/mm. The X-band output power density was 6.4 W/mm with a 53% power added efficiency (PAE).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.544-547
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• 2007

본 연구에서는 Shallow trench isolation(STI)를 형성하기 위한 과정을 제시할 것이다. 소자간 분리를 위한 전통적인 방법으로 LOCOS(Local Oxidation of Silicon) 방식이 사용되어왔으나, 소자가 미세해짐에 따라 LOCOS 방식에서 나타나는 단차와 Birds Beak이라는 횡 방향의 산화에 의한 활성 영역의 손실을 무시할 수 없게 되어 새로운 소자 분리 방법이 필요하게 되었으며 이러한 요구에 의해 도입된 Isolation 기술이 Shallow Trench Isolation(STI) 기술이다. 다양한 etching options은 중요한 부분이다. 이 경우에 trench etching의 방향은 점점 좁아지는 측면을 경사지게 하면서 협곡을 만드는 효과적인 방법을 사용할 것이다. 본 연구에서는 좁은 협곡(Shallow trench)의 절반만 시뮬레이션 될 것이다. 만약 모든 협곡의 시뮬레이션을 필요로 한다면 다변의 etching은 사용될 수 있다. STI 공정의 핵심은 trench etch를 좁게하면서 반도체 소자를 어떻게 하면 잘 분리할 수 있는가에 있다.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1924-1926
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• 2001

A novel wet release process ($\mu$ CARP - Micro Channel Assisted Release Process) for releasing an extreme large-area plate structure without etching hole is proposed and experimented. Etching holes in conventional process reduce a effective area and degrade an optical characteristics by a diffraction. In addition, as the area of a released structure increases, the stietion becomes more serious. The proposed process resolves these problems by the introduction of a micro fluidic channel beneath the structure which will be released. In this paper, a 5 mm${\times}$5mm-single crystal silicon plate structure was released by the proposed $\mu$CARP without etch holes on the structure. The variation in etching time with respect to the of the introduced micro channel is also examined. This process is expected to be beneficial for the actuator of a nano-scale data storage and the scanning mirror.

• Journal of the Semiconductor & Display Technology
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• v.13 no.2
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• pp.29-35
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• 2014

In this study general solar cell production process was complemented, with research on improvement of solar cell efficiency through surface structure and thermal annealing process. Firstly, to form the pyramid structure, the saw damage removal (SDR) processed surface was undergone texturing process with reactive ion etching (RIE). Then, for the formation of smooth pyramid structure to facilitate uniform doping and electrode formation, the surface was etched with HND(HF : HNO3 : D.I. water=5 : 100 : 100) solution. Notably, due to uniform doping the leakage current decreased greatly. Also, for the enhancement and maintenance of minority carrier lifetime, antireflection coating thermal annealing was done. To maintain this increased lifetime, front electrode was formed through Au plating process without high temperature firing process. Through these changes in two processes, the leakage current effect could be decreased and furthermore, the conversion efficiency could be increased. Therefore, compared to the general solar cell with a conversion efficiency of 15.89%, production of high efficiency solar cell with a conversion efficiency of 17.24% was made possible.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.292-292
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• 2013

최근, 자연의 기능성 표면을 모사하여 우리 생활에 응용하기 위한 연구가 활발하다. 초-발수 특성을 가지는 대표적인 예인 연꽃잎은 마이크로-나노 크기의 거친 미세돌기(papillae)를 가지고 있으며 그 위에 낮은 표면 에너지를 가지는 왁스(wax)가 발달 되어 항상 깨끗한 상태를 유지한다. 본 실험에서는 이를 모사하여 RIE (Reactive Ion Etching)방법을 이용하여 기판인 Poly silicon wafer를 Sf6가스를 사용하여 Metal mash로 거칠기를 만들어 주었고, RF-magnetron sputtering 장치를 사용하여 $6{\times}10^{-3}$ Torr의 진공도에서 낮은 표면에너지를 가지는 PTFE (polytetrafluoroethylene)를 증착하여 표면 구조와 발수특성에 대하여 조사하였다. SSME(Surface shape measurement equipment)측정결과 0.24~0.36 um RSa 값이 측정되었고, 12 uL의 Di-water로 접촉각을 측정 한 결과 RIE 10분 처리를 한 기판 위에 PTFE를 3분 증착하였을 때 가장 높은 $153^{\circ}$의 초-발수 특성이 나타났으며, 4주의 시간이 지났을 때에도 접촉각이 유지가 되었다. XPS 측정결과 초-발수 표면에서 나타나는 CF2와 CF3 피크 값이 측정되었다. Reactive Ion Etching을 이용한 PTFE 발수 특성은 방수, 스마트 윈도우, 자가세정(Self-Cleaning), 디스플레이 표시장치, 김서림 방지(Anti-Fogging), 대전방지 코팅 등에 다각적으로 응용 가능할 것이라 사료된다.

• Current Photovoltaic Research
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• v.2 no.3
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• pp.130-134
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• 2014

We have fabricated the selective emitter solar cell using double textured nanowires structure. The $40{\times}40mm2$-sized silicon substrates were textured to form the pyramid-shaped surface and the nanowires were fabricated by metal assisted chemical etching process using Ag nanoparticles, subsequently. The heavily doped and shallow emitters for selectiv eemitter solar cells were prepared through the thermal $POCl_3$ diffusion and chemical etch-back process, respectively. The front and rear electrodes were prepared following conventional screen printing method and the widths of fingers have been optimized. The selective emitter solar cell using double textured nanowires structure achieved a conversion efficiency of 17.9% with improved absorption and short circuit current density.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.99-102
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• 2002

Pinholes on the thermally grown oxide, which is called gate oxide, on silicon substrate under polysilicon layer are found and its mechanism is analyzed in this paper. The oxide under a polysilicon layer is broken during the plasma etching process of other polysilicon layer. Both polysilicon layers are separated with 0.8${\mu}{\textrm}{m}$ thick oxide deposited by CVD (Chemical Vapor Deposition). Since broken oxide points are found scattered around an arc occurrence point, it is assumed that an extremely high electric field generated near the arc occurrence point makes the gate oxide broken. 1'he arc occurrence point has been observed on the alignment key and is the mark of low yield. It is found that any arc occurrence can cause chips to fail by breaking the gate oxide, even if are occurrence points are found on scribeline.