• Journal of IKEEE
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• v.19 no.1
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• pp.41-44
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• 2015

Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.

• Transactions on Electrical and Electronic Materials
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• v.4 no.5
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• pp.10-14
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• 2003

A low-cost, large area, random, maskless texturing scheme independent of crystal orientation is expected to have significant impact on terrestrial photovoltaic technology. We investigated silicon surface microstructures formed by reactive ion etching (R IE) in Multi-Hollow cathode system. Desirable texturing effect has been achieved when radio-frequency (rf) power of about 20 Watt per one hollow cathode glow is applied for our RF Multi -Hollow cathode system. The black silicon etched surface shows almost zero reflectance in the visible region as well as in near IR region. The etched silicon surface is covered by columnar microstructures with diameters from 50 to 100 nm and depth of about 500 nm. We have successfully achieved 11.7 % efficiency of mono-crystalline silicon solar cell and 10.2 % for multi-crystalline silicon solar cell.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.2
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• pp.122-132
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• 1998

Characteristics of inductively coupled Cl2/O2 and Cl2/N2 plasmas and their effects on the formation of submicron deep trench etching of single crystal silicon have been investigated using Langmuir probe, quadrupole mass spectrometer (QMS), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM), Also, when silicon is etched with oxygen added chlorine plasmas, etch products recombined with oxygen such as SiClxOy emerged and Si-O bondings were found on the etched silicon surface. However, when nitrogen is added to chlorine, no etch products recombined with nitrogen nor Si-N bondings were found on the etched silicon surface. When deep silicon trenches were teached, the characteristics of Cl2/O2 and Cl2/N2 plasmas changed the thickness of the sidewall residue (passivation layer) and the etch profile. Vertical deep submicron trench profiles having the aspect ratio higher than 5 could be obtained by controlling the thickness of the residue formed on the trench sidewall using Cl2(O2/N2) plasmas.

• Journal of the Korean institute of surface engineering
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• v.57 no.3
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• pp.165-178
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• 2024

In semiconductor memory device manufacturing, the capability for high aspect ratio contact (HARC) etching determines the density of memory device. Given that there is no standardized definition of "high" in high aspect ratio, it is crucial to continuously monitor recent technology trends to address technological gaps. Not only semiconductor memory manufacturing companies such as Samsung Electronics, SK Hynix, and Micron but also semiconductor manufacturing equipment companies such as Lam Research, Applied Materials, Tokyo Electron, and SEMES release annual reports on HARC etching technology. Although there is a gap in technological focus between semiconductor mass production environments and various research institutes, the results from these institutes significantly contribute by demonstrating fundamental mechanisms with empirical evidence, often in collaboration with industry researchers. This paper reviews recent studies on HARC etching and the study of dielectric etching in various technologies.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.4
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• pp.749-753
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• 2010

We investigated the haze and the surface roughness of textured Si substrates etched by $XeF_2$ etching system with the etching parameters of $XeF_2$ pressure, etching time, and etching cycle. Here the haze was obtained as a function of wavelength from the measured reflectance. The haze of textured Si substrates was strongly affected by the etching parameter of etching cycle. The surface roughness of textured Si substrates was calculated with the haze and the scalar scattering theory at the wavelength of 800 nm. Then, the surface roughness was compared with that measured by atomic force microscope. The surce roughness obtained by two methods was changed with the similar tendency n terms of $XeF_2$ etching conditions.

• 한국전산유체공학회:학술대회논문집
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• 2008.03b
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• pp.703-704
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• 2008

We fabricated and tested porous silicon-based electroosmotic pumps. Compared to other pumping media, porous silicon is beneficial for obtaining comparable flow rates with much lowered electric potential, while maintaining enough mechanical properties. We fabricated porous silicon with two sided-reactive etching processes. We found higher flow rate per electric potential (consistent with previous studies) and we also found asymmetric flow rates for different pumping directions. We plan to utilize this asymmetry for AC pumping applications.

• Journal of Integrative Natural Science
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• v.2 no.3
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• pp.202-206
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• 2009

Optical images based on the porous silicon exhibiting photoluminescence have been prepared from an electrochemical etching of n-type silicon wafer (boron-doped,<100> orientation, resistivity $1{\sim}10{\Omega}-cm$) by using a beam projector. The images remained in the substrate displayed an optical images correlating to the optical pattern and could be useful for optical data storage. This provides the ability to fabricate complex optical encoding in the surface of silicon.

• Korean Journal of Materials Research
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• v.23 no.2
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• pp.116-122
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• 2013

For fabricating silicon solar cells with high conversion efficiency, texturing is one of the most effective techniques to increase short circuit current by enhancing light trapping. In this study, four different types of textures, large V-groove, large U-groove, small V-groove, and small U-groove, were prepared by a wet etching process. Silicon substrates with V-grooves were fabricated by an anisotropic etching process using a KOH solution mixed with isopropyl alcohol (IPA), and the size of the V-grooves was controlled by varying the concentration of IPA. The isotropic etching process following anisotropic etching resulted in U-grooves and the isotropic etching time was determined to obtain U-grooves with an opening angle of approximately $60^{\circ}$. The results indicated that U-grooves had a larger diffuse reflectance than V-grooves and the reflectances of small grooves was slightly higher than those of large grooves depending on the size of the grooves. Then amorphous Si:H thin film solar cells were fabricated on textured substrates to investigate the light trapping effect of textures with different shapes and sizes. Among the textures fabricated in this work, the solar cells on the substrate with small U-grooves had the largest short circuit current, 19.20 mA/$cm^2$. External quantum efficiency data also demonstrated that the small, U-shape textures are more effective for light trapping than large, V-shape textures.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1230-1235
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• 2017

We studied surface texture-etching of glass substrate by using reactive ion etching process with various working pressure (0.7~9.0 mT). With the increase in the pressure, a haze parameter, which means diffusive transmittance/total transmittance, was increased in overall wavelength regions, as measured by spectrophotometer. Also, atomic force microscopy (AFM) study also showed that the surface topography transformed from V-shaped, keen surface to U-shaped, flattened surface, which is beneficial for nanocrystalline silicon semiconductor growth with suppressing defective crack formation. The texture-etched ZnO:Al combined with textured glass exhibited pronounced haze properties that showed 60~90 % in overall spectral wavelength regions. This promising optical properties of double textured, transparent conducting substrate can be widely applied in silicon thin film photovoltaics and other optoelectronic devices.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.199-199
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• 2009

실리콘을 기판으로 하는 대부분의 태양전지에서는 표면반사에 의한 광 에너지 손실을 최소화 시키고자 습식에칭 (wet etching)에 의한 텍스쳐링 처리가 이루어진다. 그러나 습식 에칭은 공정 과정이 번거롭고 비용이 많이 든다. Inductively Coupled Plasma Etcher 장비를 이용한 플라즈마 에칭 (plasma etching)을 실리콘 표면에 적용하여 공정을 간단하고, 저렴하게 하며 반사도를 획기적으로 낮추는 기술을 개발되었다. 플라즈마 에칭으로 형성된 나노구조는 내부전반사를 일으키며 대부분의 태양에너지를 흡수한다. 나노구조는 필라(pillar)의 형태로 나타나며, 이는 플라즈마 에칭 시 발생하는 이온폭격과 에칭 측벽 식각 보호막 (SiOxFy : Silicon- Oxy-Fluoride)의 형성 때문이다. 최저의 반사도를 얻기 위해서 나노필라 형성에 기여하는 플라즈마 에칭 시간, RF bias power, SF6/O2 gas ratio의 변화에 따른 실험이 진행되었다. 플라즈마 발생 초기에는 표면의 거칠기만 증가할 뿐 필라가 형성되지 않지만 특정조건에서 4um 이상의 필라를 얻는다. 이 구조에 알루미늄 전극을 형성하여 전기적 특성을 관찰하였다. 플라즈마 에칭을 적용하여 제작된 태양전지는 표면의 반사도가 가시광 영역에서 약 1%에 불과하며, 마스크 없이 공정이 가능한 장점이 있다.