• Korean Journal of Materials Research
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• v.9 no.9
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• pp.872-877
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• 1999

The purpose of this research was to investigate the characteristics and the cleaning efficiency on HN(sub)4OH solutions added with H(sub)2O(sub)2 and surfactants. NH(sub)4OH solutions added with surfactants did not show much changes in pH and redox potential (Eh) as a function of NH(sub)4OH concentration compared with NH(sub)4OH solution. However H(sub)2O(sub)2 added NH\ulcornerOH solutions showed the decrease of pH and the increase of Eh as the concentration of NH(sub)4OH increased. The decrease of surface tension from 72 dynes/cm to 38 dynes/cm was observed in solutions added with surfactant but not in H(sub)2O(sub)2. The etch rates of silicon in NH(sub)4OH solutions(NH(sub)4OH:H(sub)2O= 1 : 5) showed at least 50 times higher than those in H(sub)2O(sub)2 and surfactant added NH(sub)4OH solutions(NH(sub)4OH:H(sub)2O(sub)2= 1 : 1 : 5) solution removed the PSL particles (0.67$\mu\textrm{m}$ in diameter) on Si wafers effectively at all temperatures investigated. NH(sub)4OH solution added with a surfactant could not remove particles at room temperature, however it was possible to remove particles at higher temperatures, 5$0^{\circ}C$ and 8$0^{\circ}C$.

• Korean Journal of Materials Research
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• v.29 no.11
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• pp.720-726
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• 2019

Recently, research on cost reduction and efficiency improvement of crystalline silicon(c-Si) photovoltaic(PV) module has been conducted. In order to reduce costs, the thickness of solar cell wafers is becoming thinner. If the thickness of the wafer is reduced, cracking of wafer may occur in high temperature processes during the c-Si PV module manufacturing process. To solve this problem, a low temperature process has been proposed. Conductive paste(CP) is used for low temperature processing; it contains Sn57.6Bi0.4Ag component and can be electrically combined with solar cells and ribbons at a melting point of $150^{\circ}C$. Use of CP in the PV module manufacturing process can minimize cracks of solar cells. When CP is applied to solar cells, the output varies with the amount of CP, and so the optimum amount of CP must be found. In this paper, in order to find the optimal CP application amount, we manufactured several c-Si PV modules with different CP amounts. The amount control of CP is fixed at air pressure (500 kPa) and nozzle diameter 22G(outer diameter 0.72Ø, inner 0.42Ø) of dispenser; only speed is controlled. The c-Si PV module output is measured to analyze the difference according to the amount of CP and analyzed by optical microscope and Alpha-step. As the result, the optimum amount of CP is 0.452 ~ 0.544 g on solar cells.

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.

• Clean Technology
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• v.7 no.1
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• pp.13-25
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• 2001

With fast advancement of fine machineries and semiconductor industries in recent decades, the ultra-cleaning of organic chemicals, submicron particles from contaminated unit equipments and products such as silicon wafers becomes one of the most important steps for further advancement of such industries. To date, two kinds of ultra cleaning techniques are used; one is the wet-cleaning and the other is the dry cleaning. In case of wet cleaning, removal of organic contaminants and submicron particles is made by DIW with additives such as $H_2O_2$, $H_2SO_4$, HCl, $NH_4OH$ and HF, etc. While the wet cleaning method is most widely adopted for various occasions, it is inevitable to discharge significant amount of toxic waste waters in environment. Dry cleaning is an alternative method to mitigate environmental pollution of the wet cleaning with maintaining comparable degree of cleaning to the wet cleaning. Although there are various concept of dry cleaning have been devised, the dry cleaning with environmentally-benign solvent such as carbon dioxide proven to show high degree of cleaning from the contaminated porous surface as well as from the bare surface. Thus, special global attention has been placing on this technique since it has important advantages of simple process schemes and no environmentally concern, etc. Thus, this article critically reviews the state-of-the-art of the supercritical fluid drying with emphasis on the thermo-physical characteristics of the supercritical solvent, environmental gains compared to other dry cleaning methods, and the generic aspects of the basic design and processing engineering.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.70-77
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• 1998

Ni/SiC Schottky diodes have been fabricated using epitaxial 4H-SiC and 6H-SiC wafers. The epitaxial n-type layers were grown on $n^{+}$ substrates, with a doping density of 4.0$\times$10$^{16}$ c $m^{-3}$ and a thickness of 10${\mu}{\textrm}{m}$. Oxide-termination has been adopted in order to obtain high breakdown voltage and low leakage current. The fabricated Ni/4H-SiC and Ni/6H-SiC Schottky barrier diodes show excellent rectifying characteristics up to the measured temperature range of 55$0^{\circ}C$. In case of oxide-terminated Schottky barrier diodes, breakdown voltage of 973V(Ni/4H-SiC) and 920V(Ni/6H-SiC), and a very low leakage current of less than 1nA at -800V has been observed at room temperature. On non-terminated Schottky barrier diodes, breakdown voltages were 430V(Ni/4H-SiC) and 160v(Ni/6H-SiC). At room temperature, SBH(Schottky Barrier Height), ideality factor and specific on-resistance were 1.55eV, 1.3, 3.6$\times$10$^{-2}$ $\Omega$.$\textrm{cm}^2$ for Ni/4H-SiC Schottky barrier diodes, and 1.24eV, 1.2, 2.6$\times$10$^{-2}$$\Omega$.$\textrm{cm}^2$/ for Ni/SH-SiC Schottky barrier diodes, respectively. These results show that both Ni/4H-SiC and Ni/6H-SiC Schottky barrier diodes are very promising for high-temperature and high power applications.s..

• Korean Journal of Materials Research
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• v.19 no.2
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• pp.61-67
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• 2009

Electrolessly deposited Co (Re,P) was investigated as a possible capping layer for Cu wires. 50 nm Co (Re,P) films were deposited on Cu/Ti-coated silicon wafers which acted as a catalytic seed and an adhesion layer, respectively. To obtain the optimized bath composition, electroless deposition was studied through an electrochemical approach via a linear sweep voltammetry analysis. The results of using this method showed that the best deposition conditions were a $CoSO_4$ concentration of 0.082 mol/l, a solution pH of 9, a $KReO_4$ concentration of 0.0003 mol/l and sodium hypophosphite concentration of 0.1 mol/L at $80^{\circ}C$. The thermal stability of the Co (Re,P) layer as a barrier preventing Cu was evaluated using Auger electron spectroscopy and a Scanning calorimeter. The measurement results showed that Re impurities stabilized the h.c.p. phase up to $550^{\circ}C$ and that the Co (Re,P) film efficiently blocked Cu diffusion under an annealing temperature of $400^{\circ}C$ for 1hr. The good barrier properties that were observed can be explained by the nano-sized grains along with the blocking effect of the impurities at the fast diffusion path of the grain boundaries. The transformation temperature from the amorphous to crystal structure is increased by doping the Re.

• Journal of the Korean Vacuum Society
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• v.14 no.2
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• pp.91-96
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• 2005

The silicon-on-insulator (SOI) wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by SRIM simulation that 65keV proton implantation is required for a SOI wafer (200nm SOI, 400nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the $6\~9\times10^{16}\;H^+/cm^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. Direct wafer bonding is performed by joining two wafers together after creating hydrophilic surfaces by a modified RCA cleaning, and IR inspection is followed to ensure a void free bonding. The wafer splitting was accomplished by annealing at the predetermined optimum condition, and high temperature annealing was then performed at $1,100^{\circ}C$ for 60 minutes to stabilize the bonding interface. TEM observation revealed no detectable defect at the SOI structure, and the interface trap charge density at the upper interface of the BOX was measured to be low enough to keep 'thermal' quality.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.475-480
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• 2017

In this paper, the conductivity of the fine pattern is improved in the insulating substrate by laser-induced forward transfer (LIFT) process. The high laser beam energy generated in conventional laser induced deposition processes induces problems such as low deposition density and oxidation of micro-patterns. These problems were improved by using a polymer coating layer for improved deposition accuracy and conductivity. Chromium and copper were used to deposit micro-patterns on silicon wafers. A multi-pulse laser beam was irradiated on a metal thin film to form a seed layer on an insulating substrate(SiO2) and electroless plating was applied on the seed layer to form a micro-pattern and structure. Irradiating the laser beam with multiple scanning method revealed that the energy of the laser beam improved the deposition density and the surface quality of the deposition layer and that the electric conductivity can be used as the microelectrode pattern. Measuring the resistivity after depositing the microelectrode by using the laser direct drawing method and electroless plating indicated that the resistivity of the microelectrode pattern was $6.4{\Omega}$, the resistance after plating was $2.6{\Omega}$, and the surface texture of the microelectrode pattern was uniformly deposited. Because the surface texture was uniform and densely deposited, the electrical conductivity was improved about three fold.

• Journal of Sensor Science and Technology
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• v.1 no.1
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• pp.23-34
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• 1992

In order to fabricate magnetoresistive sensor, Fe-Ni and Co-Ni alleys were evaporated on the slide glass and the silicon wafers. Saturation magnetic induction($B_{s}$), coercive field strength($H_{c}$) and magnetoresistance were measured for fabricated samples. The evaporated Fe-Ni thin films show that the saturation magnetic induction was 0.65 T, and coercive field strength was 0.379 A/cm, and this value was changed to 0.370 A/cm(//), 0.390 A/cm(${\bot}$), respectively after magnetic annealing. For the measurement of coercive field strength, magnetizing frequency of 1 kHz was used. For the fabricated sensor element, the change of magnetoresistance (${\Delta}R/R$) was excessively unstable due to oxidation in the process of fabrication. The evaporated Co-Ni alloy thin films show that saturation magnetic induction was 0.66 T, and coercive field strengthes were 5.895 A/cm(//), 5.898 A/cm(${\bot}$), respectively, after magnetic annelaing. The change of magnetoresistance(${\Delta}R/R$) was $3.6{\sim}3.7%$ of which value was excessively stable to room temperature. Fe-Ni thin film could have many problems due to large affinity in the process of fabrication of magnetoresistance sensor, but Co-Ni thin film could be a suitable material for fabrication of magnetoresistance sensor, because of its small affinity and definite magnetoresistance effects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.8-14
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• 2007

In this paper, $HfO_2$/Hf stacked film has been applied as the gate dielectric in MOS devices. The $HfO_2$ thin film was deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$ as precursors. Prior to the deposition of the $HfO_2$ film, a thin Hf metal layer was deposited as an intermediate layer. Round-type MOS capacitors have been fabricated on Si substrates with 2000${\AA}$-thick Al or Pt top electrode. The prepared film showed the stoichiometric components. At the $HfO_2$/Si interface, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. It seems that the intermediate Hf metal layer has a benefit for the enhancement of electric characteristics of gate dielectric in $HfO_2$/Si structure.