• Transactions on Electrical and Electronic Materials
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• 제1권1호
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.311-317
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• 2008

The measurement of dark ${\sigma}_D$, gamma-induced ${\sigma}_{\gamma}$ conductivities and the expected conductivity modulation ${\Delta}_{\sigma}$ in silicon wafers/samples is studied for developing a new technique for carrier lifetime evaluation. In this paper a simple method is introduced to find the carrier lifetime variations with the measured conductivity and conductivity modulation under dark and gamma irradiation conditions. It will be concluded that this simple method enables us to give an improved wafer evaluation, processing and quality control in the field of photovoltaic materials and other electronic devices.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.9-13
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• 2002

A polyimide-type electrostatic chuck (ESC) was fabricated for the application of holding 8-inch silicon wafers in the oxide etching equipment. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on top of thin coated copper substrates for the good electrical contacts, and the helium gas cooling technique was used for the temperature uniformity of the silicon wafers. The ESC was essentially working with an unipolar operation, which was easier to fabricate and operate compared to a bipolar operation. The chucking force of the ESC has been measured to be about 580 gf when the applied voltage was 1.5 kV, which was considered to be enough force to hold wafers during the dry etching processing. The employment of the ESC in etcher system could make 8% enhancement of the wafer processing yield.

• 비파괴검사학회지
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• 제36권1호
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• pp.1-8
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• 2016

Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

• 대한기계학회논문집A
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• 제36권5호
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• pp.505-512
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• 2012

본 논문에서 태양전지 실리콘 웨이퍼 검사를 위해 광학스캐닝 메커니즘 기반 검사장비를 개발하였다. 그 중에서 다양한 결함검사 요구와 적절한 조명조건을 만족하는 구조적 하이브리드 조명시스템을 설계하였다. 그 다음으로 실험계획법을 이용하여 구조적 하이브리드 조명시스템의 최적 조명조건을 마스터 유리와 실리콘 웨이퍼에서 선정하였다. 마스터 유리에서 최적 조명조건은 B-강, BG-강, BR-강, BGR-강 이며, 실리콘 웨이퍼에서 최적조건은 R-중-B-중 이다. 이 최적조명조건을 적용하여 실리콘 웨이퍼 표면을 검사한 결과, 핀홀, 스크래치, 치핑 등 다수의 표면결함을 정확하게 검출하였다. 구조적 하이브리드 조명시스템은 태양전지 실리콘 웨이퍼 표면결함 검사에 유용하게 사용될 수 있다.

• 한국전기전자재료학회논문지
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• 제29권8호
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• pp.455-460
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• 2016

A textured front surface is required in high efficiency silicon solar cells to reduce reflectance and to improve light trapping. Wet etching with alkaline solution is usually applied for mono crystalline silicon solar cells. However, alkali texturing method is not appropriate for multi-crystalline silicon wafers due to grain boundary of random crystallographic orientation. Accordingly, acid texturing method is generally used for multi-crystalline silicon wafers to reduce the surface reflectance. To reduce reflectivity of multi-crystalline silicon wafers, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE condition by different RF power condition (100, 150, 200, 250, 300 W).

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.264-267
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• 2007

It is important to reduce optical losses from front surface reflection to improve the efficiency of crystalline silicon solar cells. Surface texturing by isotropic etching with acid solution based on HF and $HNO_3$ is one of the promising methods that can reduce surface reflectance. Anisotropic texturing with alkali solution is not suitable for multicrystalline silicon wafers because of its various grain orientations. In this paper, we textured multicrystalline silicon wafers by simple wet chemical etching using acid solution to reduce front surface reflectance. After that, surface morphology of textured wafer was observed by Scanning Electron Microscope(SEM) and Atomic Force Microscope(AFM), surface reflectance was measured in wavelength from 400nm to 1000nm. We obtained 29.29% surface reflectance by isotropic texturing with acid solution in wavelength from 400nm to 1000nm for fabrication of multicrystalline silicon solar cells.

• 한국세라믹학회지
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• 제29권4호
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• pp.273-282
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• 1992

The effects of intrinsic and extrinsic gettering on the formation of microdefects in the wafer and on the electrical performance at near-surfaces of three different oxygen-bearing Czochralski silicon single crystal wafers were investigated by varying the combinations of the pre-heat treatments and the phosphorus diffusion through the back-surface of the wafers. The wafers which had less than 10.9 ppma of oxygen formed no gettering zones irrespective of any pre-heat treatments, while the wafers which had more than 14.1 ppma of oxygen and were treated by Low+High pre-heat treatments generated the gettering zone comprising oxygen precipitates, staking faults, and dislocation loops. The effects of extrinsic gettering by phosphorus diffusion were evident in all samples such that the minority carrier lifetimes were increased and junction leakage currents were decreased. However, the total gettering effects among the different pre-heat treatments did not necessarily correspond to the gettering structure revealed by synchrotron radiation section topograph.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.143-147
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• 2004

Surface defects and bulk defects on SOI wafers are studied. Two new metrologies have been proposed to characterize surface and bulk defects in epitaxial layer transfer (ELTRAN) wafers. They included the following: i) laser scattering particle counter and coordinated atomic force microscopy (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. The size of defect is 7.29 urn by AFM analysis, the density of defect is 0.36 /cm$^2$ at as-direct surface oxide defect (DSOD), 2.52 /cm$^2$ at ox-DSOD. A hole was formed locally without either the silicon or the buried oxide layer (Square Defect) in surface defect. Most of surface defects in ELTRAN wafers originate from particle on the porous silicon.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.