• 제목/요약/키워드: Silicon Nitride Etching

검색결과 59건 처리시간 0.029초

Fabrication of Metal Nanobridge Arrays using Sacrificial Silicon Nanowire

  • Lee, Kook-Nyung;Lee, Kyoung-Gun;Jung, Suk-Won;Lee, Min-Ho;Seong, Woo-Kyeong
    • Journal of Electrical Engineering and Technology
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    • 제7권3호
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    • pp.396-400
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    • 2012
  • Novel fabrication method of nanobridge array of various materials was proposed using suspended silicon nanowire array as a sacrificial template structure. Nanobridges of various materials can be simply fabricated by direct deposition with thermal evaporation on the top of prefabricated suspended silicon nanobridge arrays, which are used as a sacrificial structure. Since silicon nanowire can be easily removed by selective dry etching, nanobridge arrays of an intended material are finally obtained. In this paper, metal nanobridges of Ti/Au, around 50-200 nm in thickness and width, 5-20 ${\mu}m$ in length were fabricated to prove the advantages of the proposed nanowire or nanobridge fabrication method. The nanobridges of Ti/Au after complete removal of sacrificial silicon nanowire template were well-established and bending of nanobridge caused by the tensile stress was observed after silicon removing. Up to 50 nm and 10 ${\mu}m$ of silicon nanowire in diameter and length respectively was also very useful for nanowire templates.

FIB 밀링을 이용한 나노스텐실 제작 및 나노패터닝 (Fabrication of nanostencil using FIB milling for nanopatterning)

  • 정성일;오현석;김규만
    • 한국정밀공학회지
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    • 제23권3호
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    • pp.56-60
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    • 2006
  • A high-resolution shadow mask, or called a nanostencil was fabricated for high resolution lithography. This high-resolution shadowmask was fabricated by a combination or MEMS processes and focused ion beam (FIB) milling. 500 nm thick and $2{\times}2mm$ large membranes wore made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 70 nm could be made into the membrane. By local deposition through the apertures of nanostencil, nanoscale patterns down to 70 nm could be achieved.

FIB 밀링을 이용한 나노스텐실 제작 (Nanostencil fabrication using FIB milling)

  • 김규만;정성일;오현석
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2004년도 추계학술대회 논문집
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    • pp.871-874
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    • 2004
  • Fabrication of a high-resolution shadow mask, or called nanostencil, is presented. This high-resolution shadowmask is fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. 500 nm thick and 2x2 mm large membranes are made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. Subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to high resolution of FIB milling process, nanoscale apertures down to 70 nm could be made into the membrane.

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나노스텐실 제작을 위한 집속이온빔 밀링 특성 (Focused Ion Beam Milling for Nanostencil Lithography)

  • 김규만
    • 한국정밀공학회지
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    • 제28권2호
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    • pp.245-250
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    • 2011
  • A high-resolution shadow mask, a nanostencil, is widely used for high resolution lithography. This high-resolution shadowmask is often fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. In this study, FIB milling on 500-nm-thin SiN membrane was tested and characterized. 500 nm thick and $2{\times}2$ mm large membranes were made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 60 nm could be made into the membrane. The nanostencil could be used for nanoscale patterning by local deposition through the apertures.

Decrease of Global Warming Effect During Dry Etching of Silicon Nitride Layer Using C3F6O/O2 Chemistries

  • Kim, Il-Jin;Moon, Hock-Key;Lee, Jung-Hun;Jung, Jae-Wook;Cho, Sang-Hyun;Lee, Nae-Eung
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.459-459
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    • 2012
  • Recently, the discharge of global warming gases in dry etching process of TFT-LCD display industry is a serious issue because perfluorocarbon compound (PFC) gas causes global warming effects. PFCs including CF4, C2F6, C3F8, CHF3, NF3 and SF6 are widely used as etching and cleaning gases. In particular, the SF6 gas is chemically stable compounds. However, these gases have large global warming potential (GWP100 = 24,900) and lifetime (3,200). In this work, we chose C3F6O gas which has a very low GWP (GWP100 = <100) and lifetime (< 1) as a replacement gas. This study investigated the effects of the gas flow ratio of C3F6O/O2 and process pressure in dual-frequency capacitively coupled plasma (CCP) etcher on global warming effects. Also, we compared global warming effects of C3F6O gas with those of SF6 gas during dry etching of a patterned positive type photo-resist/silicon nitride/glass substrate. The etch rate measurements and emission of by-products were analyzed by scanning electron Microscopy (SEM; HITACI, S-3500H) and Fourier transform infrared spectroscopy (FT-IR; MIDAC, I2000), respectively. Calculation of MMTCE (million metric ton carbon equivalents) based on the emitted by-products were performed during etching by controlling various process parameters. The evaluation procedure and results will be discussed in detail.

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실리콘 트랜치 구조 형성용 유전체 평탄화 공정 (Dielectric Layer Planarization Process for Silicon Trench Structure)

  • 조일환;서동선
    • 전기전자학회논문지
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    • 제19권1호
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    • pp.41-44
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    • 2015
  • 소자의 집적화에 필수적인 소자 분리공정에서 화학약품의 오염 문제등을 발생시키는 화학적 기계연마기술(CMP) 공정을 사용하지 않고 벌크 finFET(fin field effect transistor) 의 트랜치 구조를 형성할 수 있는 공정에 대하여 제안하였다. 사진 감광막 도포시 발생하는 두께차이와 희생층으로 사용되는 실리콘 질화막을 사용하면 에칭 공정만을 사용하여 상대적으로 표면 위로 돌출된 부분의 실리콘 산화막 층을 에칭하는 것은 물론 finFET 의 채널로 사용되는 실리콘 트랜치 구조를 한번에 형성할 수 있는 특징을 갖는다. 본 연구에서는 AZ1512 사진 감광막을 사용하여 50 나노미터급 실리콘 트랜치 구조를 형성하는 공정을 수행하였으며 그 결과를 소개한다.

$CF_4$$O_2$혼합가스를 이용한 산화막과 질화막의 선택적 식각에 관한 연구 (Selective etch of silicon nitride, and silicon dioxide upon $O_2$ dilution of $CF_4$ plasmas)

  • 김주민;원태영
    • E2M - 전기 전자와 첨단 소재
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    • 제8권1호
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    • pp.90-94
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    • 1995
  • Reactive Ion Etching(RIE) of Si$_{3}$N$_{4}$ in a CF$_{4}$/O$_{2}$ gas plasma exhibits such good anisotropic etching properties that it is widely employed in current VLSI technology. However, the RIE process can cause serious damage to the silicon surface under the Si$_{3}$N$_{4}$ layer. When an atmospheric pressure chemical vapor deposited(APCVD) SiO$_{2}$ layer is used as a etch-stop material for Si$_{3}$N$_{4}$, it seems inevitable to get a good etch selectivity of Si$_{3}$N$_{4}$ with respect to SiO$_{2}$. Therefore, we have undertaken thorough study of the dependence of the etch rate of Si$_{3}$N$_{4}$ plasmas on $O_{2}$ dilution, RF power, and chamber pressure. The etch selectivity of Si$_{3}$N$_{4}$ with respect to SiO$_{2}$ has been obtained its value of 2.13 at the RF power of 150 W and the pressure of 110 mTorr in CF$_{4}$ gas plasma diluted with 25% $O_{2}$ by flow rate.

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Speckle Defect by Dark Leakage Current in Nitride Stringer at the Edge of Shallow Trench Isolation for CMOS Image Sensors

  • Jeong, Woo-Yang;Yi, Keun-Man
    • Transactions on Electrical and Electronic Materials
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    • 제10권6호
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    • pp.189-192
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    • 2009
  • The leakage current in a CMOS image sensor (CIS) can have various origins. Leakage current investigations have focused on such things as cobalt-salicide, source and drain scheme, and shallow trench isolation (STI) profile. However, there have been few papers examining the effects on leakage current of nitride stringers that are formed by gate sidewall etching. So this study reports the results of a series of experiments on the effects of a nitride stringer on real display images. Different step heights were fabricated during a STI chemical mechanical polishing process to form different nitride stringer sizes, arsenic and boron were implanted in each fabricated photodiode, and the doping density profiles were analyzed. Electrons that moved onto the silicon surface caused the dark leakage current, which in turn brought up the speckle defect on the display image in the CIS.

Role of gas flow rate during etching of hard-mask layer to extreme ultra-violet resist in dual-frequency capacitively coupled plasmas

  • 권봉수;이정훈;이내응
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2010년도 제39회 하계학술대회 초록집
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    • pp.132-132
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    • 2010
  • In the nano-scale Si processing, patterning processes based on multilevel resist structures becoming more critical due to continuously decreasing resist thickness and feature size. In particular, highly selective etching of the first dielectric layer with resist patterns are great importance. In this work, process window for the infinitely high etch selectivity of silicon oxynitride (SiON) layers and silicon nitride (Si3N4) with EUV resist was investigated during etching of SiON/EUV resist and Si3N4/EUV resist in a CH2F2/N2/Ar dual-frequency superimposed capacitive coupled plasma (DFS-CCP) by varying the process parameters, such as the CH2F2 and N2 flow ratio and low-frequency source power (PLF). It was found that the CH2F2/N2 flow ratio was found to play a critical role in determining the process window for ultra high etch selectivity, due to the differences in change of the degree of polymerization on SiON, Si3N4, and EUV resist. Control of N2 flow ratio gave the possibility of obtaining the ultra high etch selectivity by keeping the steady-state hydrofluorocarbon layer thickness thin on the SiON and Si3N4 surface due to effective formation of HCN etch by-products and, in turn, in continuous SiON and Si3N4 etching, while the hydrofluorocarbon layer is deposited on the EUV resist surface.

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