• Communications of the Korean Institute of Information Scientists and Engineers
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• v.3 no.1
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• pp.18-30
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• 1985

This paper describes a logical design of ternary arithmetic circuits based on T-gates. A new circuit of T-gate is proposed which is improved in the stability of operation, and a ternary adder, subtracter, multiplier and divider using the T-gates are realized. The realization of the circuits is based on the Mod-3, system and the Signed Ternary system using digit 0, 1, 2 and -1, 0, +1 as arithmetic states.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.637-637
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• 1997

In this paper, format conversion filters are proposed, which have advantages in hardware implementation compared to the ones proposed in MPEG-4 Video Verification Model. since each coefficients of the proposed filters is constrained to have less than two non-zero digits in minimal signed digit representation, multiplication of input and the coefficient can be implemented by a single adder. As a result, the proposed filters have advantages in hardware complexity and speed, compared to the filters which are usually implemented by integer multiplier or carry save adders. Six kinds of filters are proposed in MPEG-4 Video Verification Model for size conversion of 2:1, 4:1, 5:3 and 5:6. We design 5 filters for the same purpose and compare the performance. The remaining one is very simple to implement. For comparing the filtering performance, we first compare the results of sine wave frequency conversion as an indirect but meaningful comparison. Second. We compute the PSNR of the images obtained from the proposed filters and the ones proposed by MPEG, with reference to the images obtained by using double precision arithmetic and high order filter. The results show that the performance of the proposed filters is almost the same as that of the filters proposed by MPEG. In conclusion, the peroformance of the proposed filters is comparable to that of the ones in MPEG-4, while requiring lower hardware complexity and providing high operating speed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.35-41
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• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.871-880
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• 1993

Conventional binary addition rules require a carry formation and propagation to the most significant bit, and lead to serial addition. Thus, the carry progapation in a binary addition stands as a hindrance to the full utilization of parallelism optics offers, Optical adders using a modified signed-digit(MSD) number system have been proposed to eliminate the carry propagation chain states to represent the three possible digits of MSD number system must encode three different states to represent the three possible digits of MSD. In the paper, we propose the design of a parallel optical adder based on 2-bit addition rules using the method of symbolic substitution(SS).

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1187-1197
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• 1996

In this work, two-dimensional FIR digital filter is designed and simulated using research and educational CAD tools. The two-dimensional digital filter consists mainly of one-dimensional digital filter and line memory. To speed up one-dimensional digital filter, multiplications are carried out on the basis of hardwired-shifting methods by the digital filter coefficients represented in CSD formats, while carry-save adder and Manchester adder are used in addition. It is found that the designed digital filter operates up to 30 Mhz in VHDL simulation and operates normally in IRSIM simulation for the layout made by Berkeley CAD tools.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2039-2044
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• 2008

The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.