• Title/Summary/Keyword: Signal processing electronics

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Joint Demosaicking and Arbitrary-ratio Down Sampling Algorithm for Color Filter Array Image (컬러 필터 어레이 영상에 대한 공동의 컬러보간과 임의 배율 다운샘플링 알고리즘)

  • Lee, Min Seok;Kang, Moon Gi
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.4
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    • pp.68-74
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    • 2017
  • This paper presents a joint demosaicking and arbitrary-ratio down sampling algorithm for color filter array (CFA) images. Color demosaiking is a necessary part of image signal processing pipeline for many types of digital image recording system using single sensor. Also, such as smart phone, obtained high resolution image from image sensor has to be down-sampled to be displayed on the screen. The conventional solution is "Demosaicking first and down sampling later". However, this scheme requires a significant amount of memory and computational cost. Also, artifacts can be introduced or details get damaged during demosaicking and down sampling process. In this paper, we propose a method in which demosaicking and down sampling are working simultaneously. We use inverse mapping of Bayer CFA and then joint demosaicking and down sampling with arbitrary-ratio scheme based on signal decomposition of high and low frequency component in input data. Experimental results show that our proposed algorithm has better image quality performance and much less computational cost than those of conventional solution.

An Optimization on the Psychoacoustic Model for MPEG-2 AAC Encoder (MPEG-2 AAC Encoder의 심리음향 모델 최적화)

  • Park, Jong-Tae;Moon, Kyu-Sung;Rhee, Kang-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.38 no.2
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    • pp.33-41
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    • 2001
  • Currently, the compression is one of the most important technology in multimedia society. Audio files arc rapidly propagated throughout internet Among them, the most famous one is MP-3(MPEC-1 Laver3) which can obtain CD tone from 128Kbps, but tone quality is abruptly down below 64Kbps. MPEC-II AAC(Advanccd Audio Coding) is not compatible with MPEG 1, but it has high compression of 1.4 times than MP 3, has max. 7.1 and 96KHz sampling rate. In this paper, we propose an algorithm that decreased the capacity of AAC encoding computation but increased the processing speed by optimizing psychoacoustic model which has enormous amount of computation in MPEG 2 AAC encoder. The optimized psychoacoustic model algorithm was implemented by C++ language. The experiment shows that the psychoacoustic model carries out FFT(Fast Fourier Transform) computation of 3048 point with 44.1 KHz sampling rate for SMR(Signal to Masking Ratio), and each entropy value is inputted to the subband filters for the control of encoder block. The proposed psychoacoustic model is operated with high speed because of optimization of unpredictable value. Also, when we transform unpredictable value into a tonality index, the speed of operation process is increased by a tonality index optimized in high frequency range.

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Vapor Recognition Using Image Matching of Micro-Array Sensor Response from Portable Electronic Nose (휴대용 전자 후각 장치에서 다채널 마이크로 센서 신호의 영상 정합을 이용한 가스 인식)

  • Yang, Yoon-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.48 no.2
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    • pp.64-70
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    • 2011
  • Portable artificial electronic nose (E-nose) system suffers from noisy fluctuation in surroundings such as temperature, vapor concentration, and gas flow, because its measuring condition is not controled precisely as in the laboratory. It is important to develop a simple and robust vapor recognition technique applicable to this uncontrolled measurement, especially for the portable measuring and diagnostic system which are expanding its area with the improvements in micro bio sensor technology. This study used a PDA-based portable E-nose to collect the uncontrolled vapor measurement signals, and applied the image matching algorithm developed in the previous study on the measured signal to verify its robustness and improved accuracy in portable vapor recognition. The results showed not only its consistent performance under noisy fluctuation in the portable measurement signal, but also an advanced recognition accuracy for 2 similar vapor species which have been hard to discriminate with the conventional maximum sensitivity feature extraction method. The proposed method can be easily applied to the data processing of the ubiquitous sensor network (USN) which are usually exposed to various operating conditions. Furthermore, it will greatly help to realize portable medical diagnostic and environment monitoring system with its robust performance and high accuracy.

A 32${\times}$32-b Multiplier Using a New Method to Reduce a Compression Level of Partial Products (부분곱 압축단을 줄인 32${\times}$32 비트 곱셈기)

  • 홍상민;김병민;정인호;조태원
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.6
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    • pp.447-458
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    • 2003
  • A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

Development of Imaging Gamma Probe Using the Position Sensitive PMTube (위치 민감형 광전자증배관을 이용한 영상용 감마프로브의 개발)

  • Bong, Jeong-Gyun;Kim, Hui-Jung;So, Su-Gil;Kim, Han-Myeong;Lee, Jong-Du;Gwon, Su-Il
    • Journal of Biomedical Engineering Research
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    • v.20 no.1
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    • pp.107-113
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    • 1999
  • The purpose of this study was to develop a miniature imaging gamma probe with high performance that can detect small or residual tumors after surgery. Gamma probe detector system consists of NaI(Tl) scintillator, position sensitive photomultiplier tube (PSPMT), and collimator. PSPMT was optically coupled with 6.5 mm thick, 7.62 cm diameter of NaI(Tl) crystal and supplied with -1000V for high voltage. Parallel hexagonal hole collimator was manufactured for characteristics of 40-mm hole length, 1.3-mm hole diameter, and 0.22 mm septal thickness. Electronics consist of position and trigger signal readout systems. Position signals were obtained with summing, subtracting, and dividing circuit using preamplifer and amplifier. Trigger signals were obtained using summing amplifier, constant fraction discriminator, and gate and delay generator module with preamplifer. Data acquisition and processing were performed by Gamma-PF interface board inserted into pentium PC and PIP software. For imaging studies, flood and slit mask images were acquired using a point source. Two hole phantom images were also acquired with collimator. Intrinsic and system spatial resolutions were measured as 3.97 mm and 5.97 mm, respectively. In conclusion, Miniature gamma probe images based on the PSPMT showed good image quality, we conclude that the miniature imaging gamma probe was successfully developed and good image data were obtained. However, further studies will be required to optimize imaging characteristics.

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Conceptual Design Analysis of Satellite Communication System for KASS (KASS 위성통신시스템 개념설계 분석)

  • Sin, Cheon Sig;You, Moonhee;Hyoung, Chang-Hee;Lee, Sanguk
    • Journal of Advanced Navigation Technology
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    • v.20 no.1
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    • pp.8-14
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    • 2016
  • High-level conceptual design analysis results of satellite communication system for Korea augmentation satellite system (KASS) satellite communication system, which is a part of KASS and consisted of KASS uplink Stations and two leased GEO is presented in this paper. We present major functions such as receiving correction and integrity message from central processing system, taking forward error correction for the message, modulating and up converting signal and conceptual design analysis for concepts for design process, GEO precise orbit determination for GEO ranging that is additional function, and clock steering for synchronization of clocks between GEO and GPS satellites. In addition to these, KASS requires 2.2 MHz for SBAS Augmentation service and 18.5 MHz for Geo-ranging service as minimum bandwidths as a results of service performance analysis of GEO ranging with respect to navigation payload(transponder) RF bandwidth is presented. These analysis results will be fed into KASS communication system design by carrying out final analysis after determining two GEOs and sites of KASS uplink stations.

Design of a Novel Instrumentation Amplifier using Current-conveyor(CCII) (전류-컨베이어(CCII)를 사용한 새로운 계측 증폭기 설계)

  • CHA, Hyeong-Woo;Jeong, Tae-Yun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.12
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    • pp.80-87
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    • 2013
  • A novel instrumentation amplifier(IA) using positive polarity current-conveyor(CCII+) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of two CCII+, three resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into two CCII+ used voltage and current follower converts into same currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the CCII+ and used commercial op-amp LF356. Simulation results show that voltage follower used CCII+ has offset voltage of 0.21mV at linear range of ${\pm}$4V. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the gain of 60dB was 400kHz. The IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 130mW at supply voltage of ${\pm}$5V.

Implementation of Unsupervised Nonlinear Classifier with Binary Harmony Search Algorithm (Binary Harmony Search 알고리즘을 이용한 Unsupervised Nonlinear Classifier 구현)

  • Lee, Tae-Ju;Park, Seung-Min;Ko, Kwang-Eun;Sung, Won-Ki;Sim, Kwee-Bo
    • Journal of the Korean Institute of Intelligent Systems
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    • v.23 no.4
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    • pp.354-359
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    • 2013
  • In this paper, we suggested the method for implementation of unsupervised nonlinear classification using Binary Harmony Search (BHS) algorithm, which is known as a optimization algorithm. Various algorithms have been suggested for classification of feature vectors from the process of machine learning for pattern recognition or EEG signal analysis processing. Supervised learning based support vector machine or fuzzy c-mean (FCM) based on unsupervised learning have been used for classification in the field. However, conventional methods were hard to apply nonlinear dataset classification or required prior information for supervised learning. We solved this problems with proposed classification method using heuristic approach which took the minimal Euclidean distance between vectors, then we assumed them as same class and the others were another class. For the comparison, we used FCM, self-organizing map (SOM) based on artificial neural network (ANN). KEEL machine learning datset was used for simulation. We concluded that proposed method was superior than other algorithms.

Robust DNA Watermarking based on Coding DNA Sequence (부호 영역 DNA 시퀀스 기반 강인한 DNA 워터마킹)

  • Lee, Suk-Hwan;Kwon, Seong-Geun;Kwon, Ki-Ryong
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.49 no.2
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    • pp.123-133
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    • 2012
  • This paper discuss about DNA watermarking using coding DNA sequence (CDS) for the authentication, the privacy protection, or the prevention of illegal copy and mutation of DNA sequence and propose a DNA watermarking scheme with the mutation robustness and the animo acid preservation. The proposed scheme selects a number of codons at the regular singularity in coding regions for the embedding target and embeds the watermark for watermarked codons and original codons to be transcribed to the same amino acids. DNA base sequence is the string of 4 characters, {A,G,C,T} ({A,G,C,U} in RNA). We design the codon coding table suitable to watermarking signal processing and transform the codon sequence to integer numerical sequence by this table and re-transform this sequence to floating numerical sequence of circular angle. A codon consists of a consecutive of three bases and 64 codons are transcribed to one from 20 amino acids. We substitute the angle of selected codon to one among the angle range with the same animo acid, which is determined by the watermark bit and the angle difference of adjacent codons. From in silico experiment by using HEXA and ANG sequences, we verified that the proposed scheme is more robust to silent and missense mutations than the conventional scheme and preserve the amino acids of the watermarked codons.

Improvement of Address Pointer Assignment in DSP Code Generation (DSP용 코드 생성에서 주소 포인터 할당 성능 향상 기법)

  • Lee, Hee-Jin;Lee, Jong-Yeol
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.45 no.1
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    • pp.37-47
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    • 2008
  • Exploitation of address generation units which are typically provided in DSPs plays an important role in DSP code generation since that perform fast address computation in parallel to the central data path. Offset assignment is optimization of memory layout for program variables by taking advantage of the capabilities of address generation units, consists of memory layout generation and address pointer assignment steps. In this paper, we propose an effective address pointer assignment method to minimize the number of address calculation instructions in DSP code generation. The proposed approach reduces the time complexity of a conventional address pointer assignment algorithm with fixed memory layouts by using minimum cost-nodes breaking. In order to contract memory size and processing time, we employ a powerful pruning technique. Moreover our proposed approach improves the initial solution iteratively by changing the memory layout for each iteration because the memory layout affects the result of the address pointer assignment algorithm. We applied the proposed approach to about 3,000 sequences of the OffsetStone benchmarks to demonstrate the effectiveness of the our approach. Experimental results with benchmarks show an average improvement of 25.9% in the address codes over previous works.