• 대한의용생체공학회:의공학회지
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• 제19권2호
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• pp.143-152
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• 1998

In this paper, we present the performances of a Doppler system using single channel RF(Radio Frequency) sampling. This technique consists of undersampling the ultrasonic blood backscattered RF signal on a single channel. Conventional undersampling method in Doppler imaging system have to use a minimum of two identical parallel demodulation channels to reconstruct the multigate analytic Doppler signal. However, this system suffers from hardware complexity and problem of unbalance(gain and phase) between the channels. In order to reduce these problems, we have realized a multigate pulsed Doppler system using undersampling on a single channel, It requires sampling frequency at $4f_o$(where $f_o$ is the center frequency of the transducer) and 12bits A/D converter. The proposed " single-Channel RF Sampling" method aims to decrease the required sampling frequency proportionally to $4f_o$/(2k+1). To show the influence of the factor k on the measurements, we have compared the velocity profiles obtained in vitro and in vivo for different intersequence delays time (k=0 to 10). We have used a 4MHz center frequency transducer and a Phantom Doppler system with a laminar stationary flow. The axial and volumetric velocity profiles in the vessel have been computed according to factor k and have been compared. The influence of the angle between the ultrasonic beam and the flow axis direction, and the fluid viscosity on the velocity profiles obtained for different values of k factor is presented. For experiment in vivo on the carotid, we have used a data acquisition system with a sampling frequency of 20MHz and a dynamic range of 12bits. We have compared the axial velocity profiles in systole and diastole phase obtained for single channel RF sampling factor.ng factor.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2022년도 춘계학술대회
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• pp.339-343
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• 2022

본 연구에서는 VDES RF 수신기의 구조를 단순화하는 방법과 이 구조에서 국제 표준을 준수하기 위한 수신기의 이득 제어 방법을 설명하였다. 수신기의 원하는 신호와 원하지 않는 신호의 입력 레벨을 정의하고, 두 신호가 입력되면 수신기 출력에서 ADC의 포화 상태를 확인하였다. 회로 시뮬레이터에 의한 시뮬레이션 결과, 인접 채널 간섭비, 상호 변조, 차단 레벨에 대해 수신기의 출력 전력이 ADC의 SFDR 영역에 있는 것을 만족하였다. 본 연구를 통해 제안된 RF 수신기의 구조가 국제표준에 부합함을 알 수 있었다.

• Investigative Magnetic Resonance Imaging
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• 제8권1호
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• pp.42-49
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• 2004

목적 : 자기공명영상시스템에서 양자화잡음을 분석하였다. 신호대양자화잡음비를 이론적으로 유도하였고 다양한 자기공명영상시스템에서 신호대양자화잡음비를 계산하였다. 이러한 계산으로부터 고자장영상시스템에서는 양자화잡음이 전체시스템의 신호대잡음비를 결정짓는 주된 잡음원이 될 수 있음을 보였다. 하드웨어의 교체없이 양자화잡음을 줄일 수 있는 방법들을 제시하였다. 대상 및 방법 : 자기공명영상에서 사용되는 Fourier 영상기법에서는 위상 및 주파수 인코딩 방법으로 자기공명신호를 공간주파수 형태의 신호로 변환하여 측정하게 된다. 따라서 공간주파수 영역에서 발생하는 양자화잡음을 재구성된 영상에서의 신호대양자화잡음비로 나타내었다. 컴퓨터 시뮬레이션 및 실험을 통하여 유도된 식의 타당성을 보였다. 결과 : 유도된 식을 이용하여 다양한 주 자장 및 수신 시스템에 대하여 신호대양자잡음비를 계산하였다. 양자화잡음은 신호의 크기에 비례하여 증가하므로 상대적으로 신호가 큰 고자장 시스템에서 보다 큰 문제점으로 부각될 수 있다. 많은 수신 시스템에서 채택하고 있는 16 bits/샘플 양자기로는 양자화 잡음이 고자장 시스템에서 기대되는 신호대잡음비의 향상을 제한할 수 있는 주된 잡음원이 될 수 있음을 보였다. 결론 : fMRI나 spectroscopy를 위하여 자기공명영상의 주 자장은 지속적으로 높아지고 있다. 고자장에서는 신호가 커지고, susceptibility와 스펙트럼의 분리가 커져서 fMRI 나 spectroscopy에 유리한 면이 많다. 양자화잡음은 신호의 크기에 비례하여 증가하기 때문에 만약 양자기의 변환 비트가 충분히 크지 않을 경우 양자화잡음이 커져 신호의 증가에 비례하는 신호대잡음비의 향상을 이룰 수 없다. 이 논문에서는 신호대양자화잡음비를 이론적으로 유도하고, 다양한 자장의 세기 및 수신 시스템에 대하여 신호대양자화잡음비를 계산함으로써 고자장에서, 특히 상대적으로 신호가 큰 3차원영상에서 , 양자화잡음이 전체 시스템의 신호대잡음비를 제한할 수 있는 주된 잡음원이 될 수 있음을 보였다. 근원적인 해결책은 아닐 수 있으나 oversampling과 에코의 센터를 비껴가는 샘플링으로 하드웨어의 향상없이 양자화잡음을 줄일 수 있는 방법을 제시하였다.

• 한국통신학회논문지
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• 제19권11호
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• pp.2081-2093
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• 1994

본 연구에서는 DMR(Digital Microwave Radio) STM-1 신호전송을 위한 CCTTT G. 707 SDH(Synchronous Digital Hierachy) 제 1 레벨인 155Mbps 속도의 64 QAM 복조기를 설계, 구현하였다. 복조기 전반의 성능을 좌우하는 carrier recovery는 8 비트 A/D 변환기를 이용한 decision feedback carrier recovery 방식을 이용하였다. 또한 PSF(Pulse Shaping Filter)는 7차의 elliptic 필터를 이용하였다. Carrier recovery 회로는 8bit의 변환 데이터 중에서 MSB 3 bit는 데이타로 이용하고 나머지 하위 비트들은 에러성분 검출을 위한 제어신호로 이용되는 디지틀방식 및 전압제어 수정발진기와 적분기는 아나로그 방식을 이용하는 hybrid 형태로 설계, 구현하여 안정한 복조성능을 얻었다.

• Journal of Power Electronics
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• 제12권1호
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• pp.49-57
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• 2012

This paper presents performance evaluation of an Integrated Starter-Alternator (ISA) prototype with an Interior Permanent Magnet (IPM) synchronous machine under sensor-less operation. To attain a high starting torque at zero speed and in subsequent extremely low speed range, a hybrid signal injection method is proposed. At higher speed, an improved stator flux observer is used for the stator flux estimation. This observer is able to produce accurately-estimated stator flux linkage for high performance Direct Torque and Flux Control (DTFC) implementation. The sensor-less DTFC IPM synchronous machine drive takes full advantage of the capacity of the power converter and fulfills the control specifications for the ISA. The trajectory control algorithm responds rapidly and in a well behaved manner over a wide range of operating conditions. The experimental results verify the feasibility and advantages of the system.

• ETRI Journal
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• 제32권2호
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• pp.214-221
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• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

• Journal of Positioning, Navigation, and Timing
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• 제4권3호
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• pp.115-122
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• 2015

Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analogdigital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.2283-2286
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• 2003

This paper presents conservation of electrical energy in building with harmonics analysis and compensation which occur in electrical system. We use load controlling and management system in order to adjust load factor of system.The maximum demand limiting and controlling are used ,then the system can acquire the prediction and compare it to the maximum demand set point.The electrical signal analysis based on FFT technique. The harmonics are compensated by using harmonic filters.This system consists computer which works as controller, processor , analysis and database unit together with digital power meter in form of multidrop network through serial communication via RS-485.The load control system uses PLC to control load via serial communication RS-485. The A/D converter is used for sampling the electrical signals via parallel port of computer.The harmonic filters are controlled by a computer.The data of measurement such as voltage, current, power, power factor, total harmonic distortion, energy, etc., can be saved as database and analysis. The load factor is adjusted by limiting and controlling maximum demand. The load factor adjustment can reduce the cost of electric consumption and energy generation together with harmonics compensation in order to increase high efficiency of electrical system.

• 수산해양기술연구
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• 제35권3호
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• pp.328-334
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• 1999

A fish pump makes very important roles in an automation system of an aquaculture farm, thus it has been used widely in order to transfer fishes from one place to the other place automatically. In spite of its significant roles, the efforts for developing performance and promoting efficiency of the fish pump are not sufficient yet. In this paper, a method which makes the fish pump automation system is suggested. Automation of the fish pump can be accomplished by using variable voltage and variable frequency inverter system including induction motors. Especially, very simple logic to generate Pulse width Modulation(PWM) wave to control induction motor efficiently and three steps speed control method to regulate liquid quantity of the fish pump simply are suggested. Owing to the simplifies speed control and PWM wave generation technique, a cheaper microprocessor, 80C196KC, than a digital signal Processor(DSP) can be used to operate control algorithm in induction motor systems for real time control Also, a new idea of remote control for the simplifies novel inverter system by Programmable logic Controller(PLC) without special output unit, digital to analog converter(D/A), is suggested in this paper. Consequently the function of reliability, availability and serviceability of the fish pump system are developed. It will be expected to contribute expanding of application of the fish pump in aquaculture farms because the system can reduce energy consumption and some difficulties according to manual operation prominently.

• ETRI Journal
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• 제30권5호
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.