• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.13-18
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• 2010

Extreme ultraviolet (EUV) lithography using 13.5 nm wavelengths is expected to be adopted as a mass production technology for 32 nm half pitch and below. One of the new issues introduced by EUV lithography is the shadowing effect. Mask shadowing is a unique phenomenon caused by using mirror-based mask with an oblique incident angle of light. This results in a horizontal-vertical (H-V) biasing effect and ellipticity in the contact hole pattern. To minimize the shadowing effect, a refilled mask is an available option. The concept of refilled mask structure can be implemented by partial etching into the multilayer and then refilling the trench with an absorber material. The simulations were carried out to confirm the possibility of application of refilled mask in 32 nm line-and-space pattern under the condition of preproduction tool. The effect of sidewall angle in refilled mask is evaluated on image contrast and critical dimension (CD) on the wafer. We also simulated the effect of refilled absorber thickness on aerial image, H-V CD bias, and overlapping process window. Finally, we concluded that the refilled absorber thickness for minimizing shadowing effect should be thinner than etched depth.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.120-126
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• 2004

A damage-reduced trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy, which was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $O_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching. To reduce the RIE induced damage and obtain the fine shape trench corner rounding, we investigated the hydrogen annealing effect after trench formation. Silicon atomic migration on trench surfaces using high temperature hydrogen annealing was observed with atomic scale view. Migrated atoms on crystal surfaces formed specific crystal planes such as (111), (113) low index planes, instead of fully rounded comers to reduce the overall surface energy. We could observe the buildup of migrated atoms against the oxide mask, which originated from the surface migration of silicon atoms. Using this hydrogen annealing, more uniform thermal oxide could be grown on trench surfaces, suitable for the improvement of oxide breakdown.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.472-472
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• 2011

The capacitive coupled plasma (CCP) has been extensively used in the semiconductor industry because it has not only good uniformity, but also low electron temperature. But CCP source has some problems, such as difficulty in varying the ion bombardment energy separately, low plasma density, and high processing pressure, etc. In this reason, dual frequency CCP has been investigated with a separate substrate biasing to control the plasma parameters and to obtain high etch rate with high etch selectivity. Especially, in this study, we studied on the etching of $SiO_2$ by using the pulse-time modulation in the dual-frequency CCP source composed of 60 MHz/ 2 MHz rf power. By using the combination of high /low rf powers, the differences in the gas dissociation, plasma density, and etch characteristics were investigated. Also, as the size of the semiconductor device is decreased to nano-scale, the etching of contact hole which has nano-scale higher aspect ratio is required. For the nano-scale contact hole etching by using continuous plasma, several etch problems such as bowing, sidewall taper, twist, mask faceting, erosion, distortions etc. occurs. To resolve these problems, etching in low process pressure, more sidewall passivation by using fluorocarbon-based plasma with high carbon ratio, low temperature processing, charge effect breaking, power modulation are needed. Therefore, in this study, to resolve these problems, we used the pulse-time modulated dual-frequency CCP system. Pulse plasma is generated by periodical turning the RF power On and Off state. We measured the etch rate, etch selectivity and etch profile by using a step profilometer and SEM. Also the X-ray photoelectron spectroscopic analysis on the surfaces etched by different duty ratio conditions correlate with the results above.

• Clean Technology
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• v.9 no.3
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• pp.101-105
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• 2003

Plasma etching technology has been developed since it is recognized that silicon etching is very crucial in MEMS(Micro Electro Mechanical System) technology. In this study ICP(Inductive Coupled Plasma) technology was used as a new plasma etching to increase ion density without increasing ion energy, and to maintain the etching directions. This plasma etching can be used for many MEMS applications, but it has been used for PCR(Polymerase Chain Reaction) device fabrication. Platen power, Coil power and process pressure were parameters for observing the etching rate changes. Conclusively Platen power 12W, Coil power 500W, etchng/passivation cycle 6/7sec gives the etching rate of $1.2{\mu}m/min$ and sidewall profile of $90{\pm}0.7^{\circ}$, exclusively. It was concluded from this study that it was possible to minimize the environmental effect by optimizing the etching process using SF6 gas.

• Journal of Korean Society for Atmospheric Environment
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• v.14 no.E
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• pp.1-7
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• 1998

This paper presents an experimental study for understanding the indoor air quality in a room. A model room, which had a ceiling-mounted supply and a sidewall-mounted exhaust, was used to examine the effect of air exchange rate (AER) and contaminant source location (CSL) as a function of the elapsed time. A tracer gas method, using carbon monoxide tracer, gas analyzers, and a data acquisition system, was applied to study the ventilation air distribution and the tracer removal efficiency, so-called pollutant removal efficiency, in the model room. The experiment was composed of two parts; firstly the AER was varied to examine its effect on the ventilation air distribution and the ventilation effectiveness and secondly both AER and CSL were considered to determine their effect on the pollutant removal efficiency. It was found that the ventilation effectiveness in the model was proportional to AER but not linearly. It was also found that changing the CSL can improve the pollutant removal efficiency. In some cases, the efficiency improvement by increasing AER was achieved by simply changing CSL.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.322-325
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• 2005

The shrinking critical dimensions of modern technology place a heavy requirement on optimizing feature shapes at the micro- and nano scale. In addition, the use of ion beams in the nano-scale world is greatly increased by technology development. Especially, Focused ion Beam (FIB) has a great potential to fabricate the device in nano-scale. Nevertheless, FIB has several limitations, surface swelling in low ion dose regime, precipitation of incident ions, and the re-deposition effect due to the sputtered atoms. In recent years, many approaches and research results show that the re-deposition effect is the most outstanding effect to overcome or reduce in fabrication of micro and nano devices. A 2D string based simulation software AMADEUS-2D $(\underline{A}dvanced\;\underline{M}odeling\;and\;\underline{D}esign\;\underline{E}nvironment\;for\;\underline{S}putter\;Processes)$ for ion milling and FIB direct fabrication has been developed. It is capable of simulating ion beam sputtering and re-deposition. In this paper, the 2D FIB simulation is demonstrated and the characteristics of ion beam induced direct fabrication is analyzed according to various parameters. Several examples, single pixel, multi scan box region, and re-deposited sidewall formation, are given.

• Journal of the Korean Geosynthetics Society
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• v.22 no.4
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• pp.83-92
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• 2023

In this study, we conducted verification of key influencing factors during cone penetration testing using the developed Mini Cone Penetration Tester (Mini-CPT), and compared the experimental results with empirical formulas to validate the equipment. The Mini-CPT was designed to measure cone penetration resistance through a Strain Gauge, and the resistance values were calibrated using a Load Cell. Moreover, the influencing factors were verified using a model ground constituted in a soil box. The primary influencing factors examined were the boundary effect of the soil box, the distance between cone penetration points, and the cone penetration speed. For the verification of these factors, the experiment was conducted with the model ground having a relative density of 63.76% in the soil box. It was observed that the sidewall effect was considerably significant, and the cone penetration resistance measured at subsequent penetration points was higher due to the influence between penetration points. However, within the speed range considered, the effect of penetration speed was almost negligible. The measured cone penetration resistance was compared with predicted values obtained from literature research, and the results were found to be similar. It is anticipated that using the developed Mini-CPT for constructing model grounds in the laboratory will lead to more accurate geotechnical property data.

• Journal of the Semiconductor & Display Technology
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• v.3 no.3
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• pp.41-44
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• 2004

The aim of this study is the confirmation of the coating uniformity affected by the surface tension and wall attachment angle in a slit-coater model. In this work, we use the commercial code (Fluent) to solve the two-phase flow formed with air and photo resist numerically. The results show that the surface tension is the most important factor to determine the coating efficiency in the view of coating uniformity, and the coating uniformity is 2% for our slit-coater model and conditions. To improve the coating uniformity, it is in need of minimization of the sidewall effect of slit-coater.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.167-168
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• 2007

Design Rule이 작아짐에 따라 Transistor performance 향상을 위한 여러 방안중 SEG 공정이 적용되고 있으며 이에 따른 Transistor 특성 연구 결과이다. SEG공정 적용시 SEG Profile에 따라 Transistor의 Short Channel Effect 열화가 발생하였고 그 원인은 Sidewall Facet발생으로 추정되며 이를 개선시 Tr 특성이 개선됨을 확인하였다.