• Journal of the Korean Ceramic Society
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• v.47 no.5
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• pp.461-466
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• 2010

In this study, $Al_2O_3/TaAlO_4/SiO_2$ (A/TAlO/S) structures with tantalum aluminate charge trap layer were fabricated for Nand flash memory device. We evaluated the memory window and retention characteristic as the thickness of the tunnel oxide was varied among 3 nm, 4 nm, and 5 nm. All tunnel oxide thicknesses were measured by ellipsometer and TEM (Transmission Electron Microscope). The A/TAlO/S multi-layer film consisted of 5 nm tunnel oxide showed the best result of memory window of 1.57 V and retention characteristics. After annealing the 5 nm tunnel oxide A/TAlO/S multi-layer film at $900^{\circ}C$. The memory window decreased to 1.32 V. Moreover, the TEM images confirmed that the thickness of multi-layer structure decreased 14.3% after annealing and the program conditions of A/TAlO/S multi-layer film decreased from 13 V to 11 V for 100 ms. Retention properties of both as-deposited and annealed films stably maintained until to $10^4$ cycles.

• Journal of Convergence for Information Technology
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• v.9 no.3
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• pp.75-81
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• 2019

In this work, we investigated a low temperature polycrystalline silicon (LTPS) thin film transistors fabrication process on polymer layers. Dehydrogenation and activation processes were performed by a furnace annealing at a temperature of $430^{\circ}C$ for 2 hr. The crystallization of amorphous silicon films was formed by excimer laser annealing (ELA) method. The p-type device performance, fabricated by polycrystalline silicon (poly-Si) films, shows a very good performance with field effect mobility of $77cm^2/V{\cdot}s$ and on/off ratio current ratio > $10^7$. We believe that the poly-Si formed by a LTPS process may be well suited for fabrication of poly-Si TFTs for bendable panel displays such as AMOLED that require circuit integration.

• Transactions on Electrical and Electronic Materials
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• v.1 no.4
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• pp.11-15
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• 2000

This paper presents a process optimization of antireflection (AR) coating on crystalline Si solar cells. Theoretical and experimental investigations were performed on a double-layer AR(DLAR) coating of MgFe$_2$/GeO$_2$. We investigated GeO$_2$ films as an AR layer because they have a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. RF sputter grown GeO$_2$ film showed deposition temperature strong dependence. The GeO$_2$ at 400$\^{C}$ exhibited a strong (111) preferred orientation and the lowest surface roughness of 6.87 $\AA$. Refractive index of MgFe$_2$film was measured as 1.386 for the most of growth temperature. An optimized DLAR coating showed a reflectance as low as 2.04% in the wavelengths ranged from 0.4 ㎛ to 1.1 ㎛. Solar cells with a structure of MgFe$_2$/GeO$_2$/Ag/N$\^$+//p-type Si/P$\^$+//Al were investigated with the without DLAR coatings. We achieved the efficiency of solar cells greater than 15% with 3.12% improvement with DLAR coatings. Further details about MgFe$_2$,GeO$_2$ films, and cell fabrication parameters are presented in this paper.

• Journal of the Korean Vacuum Society
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• v.6 no.1
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• pp.9-19
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• 1997

The reaction mechanisms of dry cleaning with UV-excited chlorine radical for Zn, Fe and Ti trace contaminants on the Si wafer have been studied by SEM, AFM and XPS analyses in this work. The patterned Zn, Fe and Ti films were deposited on the Si wafer surface by thermal evaporation and changes in the surface morphology after dry cleaning with $Cl_2$and UV/$Cl_2$at $200^{\circ}C$ were studied by optical microscopy and SEM. In addition, changes in the surface roughness of Si wafer with the cleaning was observed by AFM. The chemical bonding states of the Zn, Fe and Ti deposited silicon surface were observed with in-line XPS analysis. Zn and Fe were easily cleaned in the form of volatile zinc-chloride and iron-chloride as verified by the surface morphology changes. Ti which forms involatile oxides was not easily removed at room temperature but was slightly removed by UV/$Cl_2$at elevated temperature of $200^{\circ}C$. It was also found that the surface roughness of the Si wafer increased after $Cl_2$and UV/$Cl_2$cleaning. Therefore, the metallic contaminants on the Si wafer can be easily removed at lower temperature without surface damage by a continuous process using wet cleaning followed by UV/$Cl_2$dry cleaning.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.832-834
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• 1992

Using the PECVD method, the silicon nitride films were deposited by changing the $SiH_4/NH_3$ gas flow ratio from 0.2 to 1.4 at an interval of 0.2, AES, FTIR, and Spectroscopic Ellipsomter were used to analyze the film composition and structure, the refractive index, and the deposition rate. Also the C-V analysis was used to estimate the memory performance in the capacitor type MNOS memory devices, which utilized native oxide as the tunneling barrier, with the silicon nitride by the above deposition conditions. As a result, it was confirmed that the performance of MNOS memory devices with PECVD silicon nitride was comparable to that with LPCVD or APCVD silion nitride.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.248-254
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• 1998

DLC(Diamond-Like-Carbon) thin film, one of the solid state amorphous carbon films, has been deposited by the method of PECVD (Plasma Enhanced Chemical Vapor Deposition). The structural features have been characterized using both FT-IR Spectroscopy and Raman Scattering. The film is considered to consist of microcrystalline diamond domains and graphitelike carbon domains, which are interconnected by hydrogenated $sp^3$ tetrahedral carbons. This shows a good agreement with the results by I-Vmeasurements. In I-Vstudy, the sudden increase of current has been observed and this phenomenon is understood to be due to the tunneling effect between graphitelike domains. A characteristic feature related to the $\beta$-SiC has been identified in the study of Raman Scattering for the very thin film, which suggests that a buffer layer forms at the interface of the Si substrate and the carbon film.

• Korean Journal of Materials Research
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• v.5 no.2
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• pp.197-202
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• 1995

The surface morphology and grain growth of amophous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD) have been investigated as a function of deposition and in sltu annealing condition. The film deposited at the amorphous to polycrystalline transition temperature has an extra-rough, rugged surface with (311) t.exture. At the same deposition temperature, the grain structure tends to shirr. from the polycrystalline to the amorphous phase with increasing the film thickness. It is found that nucleation of a-Si during in situ annealing at the transition temperature without breaking the vacuum starts to occur from surface Si atom migration in contrast to a heterogeneous nucleation during film deposition.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.338-341
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• 1995

The surface properties after plasma etching of Al(Si, Cu) solutions using the chemistries of chlorinated and fluorinated gases with varying the etching time have been investigated using X-ray Photoelectron Spectroscopy. Impurities of C, Cl, F and O etc are observed on the etched Al(Si, Cu) films. After 95% etching, aluminum and silicon show metallic states and oxized (partially chlorinated) states, copper shows Cu metallic states and Cu-Clx(x$CuCl_x$ (x$CuCl_x$ (1

• Korean Journal of Materials Research
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• v.9 no.2
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• pp.144-148
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• 1999

We have studied the deposition characteristics of thick silicon dioxide film on Si substrate by $O_3$/TEOS APCVD(Atmospheric Pressure Chemical Vapor Deposition). The effect of deposition parameters such as the distance between showerhead and substrate, deposition temperature, TEOS flow rate and $O_3$/TEOS ratio on deposition rate, surface morphology, and properties of films as investigated. As deposition temperature increased, deposition rate decreased but the surface morphology and adhesion of film to substrate improved. As the distance between showerhead and substrate decreased, the deposition rate increased. Etching rate using the BOE increased as TEOS flow rate increased, but was independent of$ O_3$/TEOS ratio. Deposition rate of $5\mu\textrm{m}$/hour was obtained under the condition that the distance between showerhead and substrate was 5mm and the deposition temperature was $370^{\circ}C$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.