• Electronics and Telecommunications Trends
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• v.27 no.5
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• pp.109-125
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• 2012

액정 디스플레이의 산업 규모는 놀라운 속도로 확대되고 있다. 그 원동력이 된 것이 박막 트랜지스터(Thin Film Transistor: TFT) 기술의 발전에 있다. 비정질 실리콘(Amorphous Silicon: a-Si) TFT 기술은 대형 액정 TV를 탄생시키고, 저온 폴리실리콘 TFT는 휴대전화 등의 중소형 디스플레이와 AMOLED의 핵심 기술이 되었다. 또한 다양한 TFT 기술 seeds가 계속해서 출현하여 정보 인프라와 생활 스타일에 맞춘 새로운 정보기기의 출현을 예감시키고 있다. 새로운 응용제품의 요구는 새로운 기술 개발의 견인차가 되고 있다. 최근에는 이러한 요구에 따라 산화물 TFT, 마이크로 결정실리콘(microcrystalline Si: ${\mu}c-Si$) TFT, 유기물 TFT 등의 기술도 활발하게 연구개발되고 있다. 본고에서는 지금까지의 TFT 기술 개발의 발전사를 뒤돌아보고 지금부터의 발전 방향을 박막 트래지스터 기술 이노베이션 관점으로부터 전망하였다.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.158-161
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• 1991

A new analytical expression for the temperature variation characteristics of hydrogenerated amorphous silicon (a-si:H) thin film transistors, between 223K and 433K, is presented and experimentally virified. The result show that the experimental transfer and output characteristics at several temperatures are easily modeled between $-50^{\circ}C\;and\;90^{\circ}C$. The model is based on three function obtained from the experimental data of $I_D$ versus $V_G$. Theoretical results comfirm the simple form of the model in terms of the device geometry. It was determined that as the temperature increaseed, the saturated drain current increased.

• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.62-64
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• 2004

초고속 RF IC의 핵심소자인 SiGe에피텍시층을 가진 이종양극트란지스터 (hetero junction bipolar transistor: HBT)를 0.35um급 CMOS공정으로 제작하였다. 이때 IOW $V_{BE}$영역에서의 Current Gain의 선형성을 향상시키기 위하여 Capping 실리콘의 두께를 200과 300${\AA}$으로 나누고 EDR (Emitter Drive-in RTA)의 온도와 시간을 900$\~$1000C, 0$\~$30sec로 각각 변화시키면서 최적조건을 알아보았다. 실험범위 내에서의 최적공정조건은 300${\AA}$의 capping 실리콘과 975C-30sec의 EDR조건이었다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.135-140
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• 2019

In this paper, a frequency split type broadband drive amplifier operating in the L, S and C bands was designed and fabricated. Transistor is difficult to efficiently use when the fractional bandwidth of the drive amplifier is more than 100%, In particular, the characteristics of the driving amplifier are important for operating the power amplifier in which the characteristics of the output power and the efficiency are sensitively changed according to the frequency band. A frequency split methods was applied to maximize the bandwidth of a drive amplifier and to divide the output of the drive amplifier into low band and high band so that the transistor of the power amplifier located at the rear of the drive amplifier can be efficiently used. The designed drive amplifier was fabricated in GaAs HBT technology and 9-layer SiP, and verified by the measurements. The fabricated drive amplifier shows a gain of more than 8 dB and an output power of more than 15 dBm in the operating frequency range.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.221-225
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• 2003

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.94-97
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• 2017

Amorphous Si has been used for data processing circuits in flat panel displays. However, low mobility of the amorphous Si is a limiting factor for the data transmission speed. Metal oxides such as ZnO have been studied to replace the amorphous Si. ZnO is a wide bandgap (3.3 eV) semiconductor with high mobility and good optical transparency. When ZnO is grown by sputtering with $O_2$ as an oxidizer, there can be many ion species arising from $O_2$ decomposition. $O^+$, $O_2{^+}$, and $O^-$ ions are expected to be the most abundant species, and it is not clear which one contributes to the ZnO growth. We applied alternating substrate voltage (0 V and -70 V) during sputtering growth. We studied changes in transistor characteristics induced by the voltage switching. We also compared ZnO grown by dc and rf sputtering. ZnO film was grown at $450^{\circ}C$ substrate temperature. ZnO thin-film transistor grown with these methods showed $7.5cm^2/Vsec$ mobility, $10^6$ on-off ratio, and -2 V threshold voltage.

• Electrical & Electronic Materials
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• v.9 no.1
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.66-66
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• 1999

최근 들어 다결정 SiGe은 MOS(Metal-Oxide-Semiconductor)에서 기존에 사용되던 다결정 Si 공정과의 호환성 및 여러 장점으로 인하여 다결정 Si 대안으로 많은 연구가 진행되고 있다. 고농도로 도핑된 P type의 다결정 SiGe은 Ge의 함량에 따른 일함수의 조절과 낮은 비저항으로 submicrometer CMOS 공정에서 게이트 전극으로 이용하려는 연구가 진행되고 있으며, 55$0^{\circ}C$ 이하의 낮은 온도에서도 증착이 가능하고, 도펀트의 활성화도가 높아서 TFT(Thin Film Transistor)에서도 유용한 재료로 검토되고 있다. 현재까지 다결정 SiGe의 증착은 MBE, APCVD, RECVD. HV/LPCVD 등 다양한 방법으로 이루어지고 있다. 이중 HV/LPCVD 방법을 이용한 증착은 반도체 공정에서 게이트 전극, 유전체, 금속화 공정 등 다양한 공정에서 사용되고 있는 방법으로 현재 사용되고 있는 반도체 공정과의 호환성의 장점으로 다결정 SiGe 게이트 전극의 증착 공정에 적합하다고 할 수 있다. 본 연구에서는 HV/LPCVD 방법을 이용하여 게이트 전극으로의 활용을 위한 다결정 SiGe의 증착 메카니즘을 분석하고 Ex-situ implantation 후 열처리에 따라 나타나는 활성화 정도를 분석하였다. 도펀트를 첨가하지 않은 다결정 SiGe을 주성엔지니어링의 EUREKA 2000 장비를 이용하여, 1000$\AA$의 열산화막이 덮혀있는 8 in 웨이퍼에 증착하였다. 증착 온도는 55$0^{\circ}C$에서 6$25^{\circ}C$까지 변화를 주었으며, 증착압력은 1mtorr-4mtorr로 유지하였다. 낮은 증착압력으로 인한 증착속도의 감소를 방지하기 위하여 Si source로서 Si2H6를 사용하였으며, Ge의 Source는 수소로 희석된 10% GeH4와 100% GeH4를 사용하였다. 증착된 다결정 SiGe의 Ge 함량은 RBS, XPS로 분석하였으며, 증착된 박막의 두께는 Nanospec과 SEM으로 관찰하였다. 또한 Ge 함량 변화에 따른 morphology 관찰과 변화 관찰을 위하여 AFM, SEM, XRD를 이용하였으며, 이온주입후 열처리 온도에 따른 활성화 정도의 관찰을 위하여 4-point probe와 Hall measurement를 이용하였다. 증착된 다결정 SiGe의 두게를 nanospec과 SEM으로 분석한 결과 Gem이 함량이 적을 때는 높은 온도에서의 증착이 더 빠른 증착속도를 나타내었지만, Ge의 함량이 30% 되었을 때는 온도에 관계없이 일정한 것으로 나타났다. XRD 분석을 한 결과 Peak의 위치가 순수한 Si과 순수한 Ge 사이에 존재하는 것으로 나타났으며, ge 함량이 많아짐에 따라 순수한 Ge쪽으로 옮겨가는 경향을 보였다. SEM, ASFM으로 증착한 다결정 SiGe의 morphology 관찰결과 Ge 함량이 높은 박막의 입계가 다결정 Si의 입계에 비해 훨씬 큰 것으로 나타났으며 근 값도 증가하는 것으로 나타났다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.5
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• pp.237-241
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• 2004

Amorphous silicon (a-Si) films are used in a broad range of solar cell, flat panel display, and sensor. Because of the greater ease of deposition and lower processing temperature, thin films are widely used for thin film transistors (TFTs). However, they have lower stability under the exposure of visible light and because of their low field effect mobility ($\mu$$_{FE}$ ) , less than 1 c $m^2$/Vs, they require a driving IC in the external circuits. On the other hand, polycrystalline silicon (poly-Si) thin films have superiority in $\mu$$_{FE}$ and optical stability in comparison to a-Si film. Many researches have been done to obtain high performance poly-Si because conventional methods such as excimer laser annealing, solid phase crystallization and metal induced crystallization have several difficulties to crystallize. In this paper, a new crystallization process using a molybdenum substrate has been proposed. As we use a flexible substrate, high temperature treatment and roll-to-roll process are possible. We have used a high temperature process above 75$0^{\circ}C$ to obtain poly-Si films on molybdenum substrates by a rapid thermal annealing (RTA) of the amorphous silicon (a-Si) layers. The properties of high temperature crystallized poly-Si studied, and poly-Si has been used for the fabrication of TFT. By this method, we are able to achieve high crystal volume fraction as well as high field effect mobility.