• Journal of Information Display
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• v.6 no.3
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• pp.12-17
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• 2005

The need for low cost, flexible, thin film transistor (TFT) display backplanes has focused attention on new processing techniques and materials. We report the development of TFT backplane technology based entirely on jet-printing, using a combination of additive and subtractive processing, to print active materials or etch masks. The technique eliminates the use of photolithography and has the potential to reduce the array manufacturing cost. The printing technique is demonstrated with both amorphous silicon and polymer semiconductor TFT arrays, and we show results of small prototype displays.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.221-225
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• 2001

In the paper, we report on the DC and Thermal effect of the GaN based HFET. A physics-based a model was applied and found to be useful for predicting the DC performance and Thermal effect of the GaN based HFET by Various substrate. The performance of device on the sapphire substrates is found to be significantly improve compared with that of a device with an sapphire substrate. The peak drain current of the device achieved at HFET on the SiC substrate

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.268-268
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• 2010

단일벽 탄소 나노튜브(SWCNT)는 그 뛰어난 전기적, 물리적 특성 때문에 반도체 공정에 있어서 중요한 p-type 채널 물질로 꼽히고 있다. 본 연구에서는 SWCNT를 성장하여 이를 이용한 전계효과 트랜지스터를 제작하고 또한, 부분적인 폴리머의 코팅으로 타입을 변화하는 연구를 보이고자 한다. Ferritin용액을 DI-water에 2000배 희석하여 SiO2 기판 위에 뿌린 뒤 Methanol을 이용하여 기판 표면에 촉매가 붙어있게 한다. 이 기판을 $900^{\circ}C$로 가열하여 유기물질을 제거한 뒤 화학 기상 증착(Chemical Vapor Deposition)방법으로 SWCNT를 성장하게 된다. 이렇게 성장된 SWCNT는 촉매의 농도에 비례하는 밀도를 가지게 되며 이 위에 전극을 증착하고 back-gate를 설치하여 FET를 제작한다. 메탈릭한 SWCNT는 breakdown 공정을 통하여 제거한 뒤, 전자 농도가 높은 NADH를 전체적으로 코팅을 한다. NADH는 기존의 다른 폴리머(polyethyleneimine: PEI)에 비교하여 코팅 후 전자 제공 효과가 크며 그 성질의 재현성이 높고 공기 중에서 안정성을 유지하는 능력이 있다. 이러한 NADH의 코팅으로 n-type으로의 SWCNT FET를 제작하였으며 type conversion 현상을 이용하면 국부적인 NADH의 코팅으로 homojunction-diode의 제작 등 다양한 소자의 제작에 적용될 것으로 예상한다.

• Journal of the Korean Ceramic Society
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• v.38 no.5
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• pp.474-478
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• 2001

유기 화학 기상 증착법(MOCVD)을 이용하여 반응기체 $O_2$의 양 및 Y와 Mn의 운반기체 비(Y/Mn)를 변화시켜가며 Si(100) 기판 위에서 MFSFET(metal-ferroelectric-semiconductor field effect transistor) 구조의 YMnO$_3$박막을 증착하였다. 반응기체 $O_2$의 양이 150sccm일 때 Y/Mn=2와 3인 경우 단일상의 육방정계 YMnO$_3$박막이 형성되었다. YMnO$_3$박막의 전기적 특성은 사방정계 YMnO$_3$박막에서는 나타나지 않았으나, 육방정계 YMnO$_3$박막의 경우 결정립 크기에 영향을 받아 단일상의 육방정계 YMnO$_3$박막 중 결정립 크기가 150nm~200nm(Y/Mn=2)인 경우에는 잔류분극이 100nC/$ extrm{cm}^2$인 P-E 이력곡선의 특성을 나타내었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.6
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• pp.512-518
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• 2006

In this paper, we investigated the deposition of pentacene thin film on a large area substrate by Organic Vapor Phase Deposition(OVPD) and applied it to fabrication of Organic Thin Film Transistor(OTFT). We extracted the optimum deposition conditions such as evaporation temperature of $260^{\circ}C$, carrier gas flow rate of 10 sccm and chamber vacuum pressure of 0.1 torr. We fabricated 72 OTFTs on the 4 inch size Si Wafer, Which produced the average mobility of $0.1{\pm}0.021cm^2/V{\cdot}s$, average subthreshold slope of 1.04 dec/V, average threshold voltage of -6.55 V, and off-state current is $0.973pA/{\mu}m$. The overall performance of pentacene TFTs over 4 ' wafer exhibited the uniformity with the variation less than 20 %. This proves that OVPD is a suitable methode for the deposition of organic thin film over a large area substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.221-225
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• 2001

In the paper, we report on the DC and Thermal effect of the GaN based HFET. A physics-based a model was applied and found to be useful for predicting the DC performance and Thermal effect of the GaN based HFET by Various substrate. The performance of device on the sapphire substrates is found to be significantly improve compared with that of a device with an sapphire substrate. The peak drain current of the device achieved at HFET on the SiC substrate

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.125-130
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• 2009

This paper reviews the characteristics technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• Transactions on Electrical and Electronic Materials
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• v.18 no.3
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• pp.141-143
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• 2017

Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at $500^{\circ}C$. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from $14.77cm^2/Vs$ to $35.59cm^2/Vs$ simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.2
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• pp.133-140
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• 2024

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.70-70
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• 2003

금속용액을 이용하여 측면고상결정화 시킨 다결정 실리콘 박막내의 고각입계를 줄이기 위해 서 고온열처리를 실시하였다. SEM과 TEM을 이용하여 다결정 실리콘내의 바늘모양의 결정립의 폭의 증가를 관찰하였고, 결정 립내의 결함이 감소를 관찰하였다. 그리고 결정화된 다결정 실리콘의 표면 거칠기를 AFM이용하여 퍼니스에서 53$0^{\circ}C$에서 25시간 동안 결정화 시킨 시편과 이후 80$0^{\circ}C$에서 40분간 추가 고온 열처리시킨 시편을 비교한 결과 6.09$\AA$에서 4.22$\AA$으로 개선되었음을 확인할 수 있었다. 박막내의 금속에 의한 오염을 줄이기 위해 금속의 농도를 줄인 금속용액을 결정화에 사용하였다. 이때 저농도 금속용액을 사용하여 측면결정화시킨 다결정 실리콘 박막내의 소각입계를 이루는 결정립군의 크기가 고농도 금속용액을 이용하여 측면결정화시킨 경우보다 증가함을 확인 할 수 있었다. 박막트랜지스터를 제작하여 트랜지스터의 전기적특성을 살펴보았다. 전계이동도가 80$0^{\circ}C$ 고온 열처리에 의해서 53$\textrm{cm}^2$/Vsec 에서 95$\textrm{cm}^2$/Vsec 로 상승하였는데 이는 고온열처리에 의해서 측면결정화된 다결정 실리콘내의 트랩 밀도가 2.2$\times$$10^{12}$/$\textrm{cm}^2$ 에서 1.3$\times$$10^{12}$$\textrm{cm}^2$로 감소하였기 때문이다.