• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.341.1-341.1
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• 2014

In the advanced material for the next generation display device, transparent amorphous oxide semiconductors (TAOS) are promising materials as a channel layer in thin film transistor (TFT). The TAOS have many advantages for large-area application compared with hydrogenated amorphous silicon TFT (a-Si:H) and organic semiconductor TFT. For the reasonable characteristics of TAOS, The a-IGZO has the excellent performances such as low temperature fabrication (R.T~), high mobility, visible region transparent, and reasonable on-off ratio. In this study, we investigated how the electric characteristics and physical properties are changed as various oxygen ratio when magnetron sputtering. we analysis a-IGZO film by AFM, EDS and I-V measurement. decreasing the oxygen ratio, the threshold voltage is shifted negatively and mobility is increasing. Through this correlation, we confirm the effect of oxygen ratio. We fabricated the bottom-gate a-IGZO TFTs. The gate insulator, SiO2 film was grown on heavily doped silicon wafer by thermal oxidation method. a-IGZO channel layer was deposited by RF magnetron sputtering. and the annealing condition is $350^{\circ}C$. Electrode were patterned Al deposition through a shadow mask(160/1000 um).

• Journal of Biomedical Engineering Research
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• v.29 no.5
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• pp.392-399
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• 2008

Thin-film transistor (TFT) arrays for an x-ray detector require quite different design concept from that of the conventional active-matrix liquid crystal devices (AM-LCDs). In this paper anew design of TFT array which uses only SiNx for passivation layer is described to meet the detector performance and the product availability simultaneously. For the purpose of optimizing the design parameters of the TFT array, a Spice simulation was performed. As a result, some parameters, such as the TFT width, the data line capacitance, and the storage capacitance, were able to be fixed. The other parameters were decided within a permissible range of the TFT process especially the photolithography process and the wet etch process. Then we adapted the TFT array which had been produced by the proposed design to our prototype model (FDXD-1417 and evaluated it clinically by comparing with a commercial model (EPEX, Hologic, Beford, USA). The results say that our prototype model is slightly better than EPEX system in chest PA images. So we can prove the technical usefulness and the commercial values of the proposed TFT design.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.252-252
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• 2011

최근 주목받고 있는 amorphous gallium-indium-zinc-oxide (a-GIZO) thin film transistors (TFTs)는 수소가 첨가된 비정질 실리콘 TFT에 비해 높은 이동도와 뛰어난 전기적, 광학적 특성에 의해 큰 주목을 받고 있다. 또한 넓은 밴드갭을 가지므로 가시광 영역에서 투명한 특성을 보이고, 플라스틱 기판 위에서 구부러지는 성질에 의해 플랫 패널 디스플레이나 능동 유기 발광소자 (AM-OLED), 투명 디스플레이에 응용되고 있다. 뿐만 아니라, 일반적인 Poly-Si TFT는 자체적으로 가지는 결정성에 의해 대면적화 시 균일성이 좋지 못하지만 GIZO는 비정질상 이기 때문에 백플레인의 대면적화에 유리하다는 장점이 있다. 이러한 TFT를 제작하기 전, 전기적 특성에 대한 정보를 얻거나 예측하는 것이 중요한데, 이에 따라 고안된 구조가 바로 metal point contact FET (pseudo FET)이다. pseudo FET은 소스/드레인 전극을 따로 증착할 필요 없이 채널을 증착한 후, 프로브 탐침을 채널의 표면에 적당한 압력으로 접촉시켜 전하를 공급하는 소스와 드레인처럼 동작시킬 수 있다. 따라서 소스/드레인을 증착하거나 lithography와 같은 추가적인 공정을 요구하지 않아 소자의 특성을 보다 간단하고 수월하게 분석할 수 있다는 장점이 있다. 본 연구에서는 p-type 기판위에 100nm의 oxidation SiO2를 게이트 절연막으로 사용하는 a-GIZO pseudo FET를 제작하였다. 소자 제작 후, 열처리 온도에 따른 전기적 특성을 분석하였고, 열처리 조건은 30분간 N2 분위기에서 실시하였다. 열처리 후 전기적 특성 분성 결과, 450oC에서 가장 낮은 subthreshold swing 값과 게이트 전압의 더블 스윕 후 문턱 전압의 변화가 거의 없음을 확인하였다.

• Korean Journal of Materials Research
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• v.24 no.3
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• pp.140-144
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• 2014

The contact mechanism of devices is usually researched at electrode contacts. However, the contact between a dielectric and channel at the MOS structure is more important. The graphene was used as a channel material, and the thin film transistor with MOS structure was prepared to observe the contact mechanism. The graphene was obtained on Cu foil by the thermal decomposition method with $H_2$ and $CH_4$ mixed gases at an ambient annealing temperature of $1000^{\circ}C$ during the deposition for 30 min, and was then transferred onto a $SiO_2/Si$ substrate. The graphene was doped in a nitrogen acidic solution. The chemical properties of graphene were investigated to research the effect of nitric atoms doping. The sheet resistance of graphene decreased after nitrogen acidic doping, and the sheet resistance decreased with an increase in the doping times because of the increment of negative charge carriers. The nitric-atom-doped graphene showed the Ohmic contact at the curve of the drain current and drain voltage, in spite of the Schottky contact of grapnene without doping.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.7-10
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• 2005

[ $SiO_{2}$ ] or SiON is usually deposited and annealed after formation of silicide in real transistor fabrication processes. Nickel silicide and nickel silicide with Co interlayer were annealed at 650$^{\circ}C$ for 30 min with silica top layer in this study to investigate its thermal stability. SEM, XPS, and FPP(four point probe) were employed for the investigation. Nickel silicide with Co interlayer showed improved thermal stability. Co interlayer seems to play a key role to the stability of nickel silicide.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.151-151
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• 2010

In this paper, the electrically properties of nonvolatile memory (NVM) using multi-stacks gate insulators of oxide-nitride-oxynitride (ONOn) and active layer of the low temperature polycrystalline silicon (LTPS) were investigated. From hydrogenated amorphous silicon (a-Si:H), the LTPS thin films with high crystalline fraction of 96% and low surface's roughness of 1.28 nm were fabricated by the metal induced crystallization (MIC) with annealing conditions of $650^{\circ}C$ for 5 hours on glass substrates. The LTPS thin film transistor (TFT) or the NVM obtains a field effect mobility of ($\mu_{FE}$) $10\;cm^2/V{\cdot}s$, threshold voltage ($V_{TH}$) of -3.5V. The results demonstrated that the NVM has a memory window of 1.6 V with a programming and erasing (P/E) voltage of -14 V and 14 V in 1 ms. Moreover, retention properties of the memory was determined exceed 80% after 10 years. Therefore, the LTPS fabricated by the MIC became a potential material for NVM application which employed for the system integration of the panel display.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• Journal of the Korean Applied Science and Technology
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• v.27 no.2
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• pp.137-143
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• 2010

Oxide semiconductors Thin-film transistors are an exemplified one owing to its excellent ambient stability and optical transparency. In particular zinc oxide (ZnO) has been reported because It has stability in air, a high electron mobility, transparency and low light sensitivity, compared to any other materials. For this reasons, ZnO TFTs have been studied actively. Furthermore, we expected that would be satisfy the demands of flexible display in new generation. In order to do that, ZnO TFTs must be fabricated that flexible substrate can sustain operating temperature. So, In this paper we have studied low-temperature process of zinc oxide(ZnO) thin-film transistors (TFTs) based on silicon nitride ($SiN_x$)/cross-linked poly-vinylphenol (C-PVP) as gate dielectric. TFTs based on oxide fabricated by Low-temperature process were similar to electrical characteristics in comparison to conventional TFTs. These results were in comparison to device with $SiN_x$/low-temperature C-PVP or $SiN_x$/conventional C-PVP. The ZnO TFTs fabricated by low-temperature process exhibited a field-effect mobility of $0.205\;cm^2/Vs$, a thresholdvoltage of 13.56 V and an on/off ratio of $5.73{\times}10^6$. As a result, We applied experimental for flexible PET substrate and showed that can be used to ZnO TFTs for flexible application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.