• 대한전자공학회논문지SD
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• 제40권7호
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• pp.481-485
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• 2003

25㎛ 두께의 폴리이미드 박핀 기판을 glass 기판에 부착하여 최대 온도 150℃에서 비정질 실리콘 TFT를 제작하였다. 본 논문은 plastic 기판 위에 TFT가 제작되는 공정 절차를 요약하고 glass 위에 제작된 TFT와 ON/OFF 전달특성과 전계효과 이동도를 서로 비교해 보았다. a-SiN:H 코팅층은 plastic 기판의 표면 거칠기를 감소시키는 중요한 역할을 하여 TFT의 누설전류를 감소시키고 전계효과 이동도를 증가시켰다. 따라서 a-SiN:H 코팅층을 이용하여 plastic 기판에 양철의 TFT를 제작하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.257.2-257.2
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• 2015

In this paper, we report on the 10.33% efficient thin film/bulk tandem solar cells with the top cell made of amorphous silicon thin film and p-type bulk crystalline silicon bottom cell. The tunneling junction layers were used the doped nanocrystalline Si layers. It has to allow an ohmic and low resistive connection. For player and n-layer, crystalline volume fraction is ~86%, ~88% and dark conductivity is $3.28{\times}10-2S/cm$, $3.03{\times}10-1S/cm$, respectively. Optimization of the tunneling junction results in fill factor of 66.16 % and open circuit voltage of 1.39 V. The open circuit voltage was closed to the sum of those of the sub-cells. This tandem structure could enable the effective development of a new concept of high-efficiency and low cost cells.

• Applied Microscopy
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• 제21권2호
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• pp.57-66
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• 1991

The main purpose of this paper was to investigate the change of rapidly solidified microstructures and dispersoid behavior according to heat-treatment in the Al-Fe-V-Si-(Mn) alloys. It was found that (111) preferred orientation identified by X-ray diffraction and fine subgrain/large grain were observed in the rapidly solidified Al-Fe-V-Si-(Mn) alloys. Cell boundary of the zone A was composed of the microcrystalline, whereas that of the zone B was amorphous. Decomposition of the Al-Fe-V-Si-(Mn) alloys occurred at about $300^{\circ}C$. These alloys exhibited excellent thermal stability at the elevated temperature. Microstructure of the zone B was more stable than that of the zone A. The spherical dispersoid and 5-fold symmetry phase was also more thermally stable than the amorphous structure of cell boundary.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.739-742
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• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.579-582
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• 2000

This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.

• Journal of Information Display
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• 제4권1호
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• pp.1-8
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• 2003

Recent progress in both low pretilt and high pretilt defect free C1 surface stabilized ferroelectric liquid crystal (SSFLC) devices is reviewed. First, by numerical calculation to investigate the balance between surface azimuthal anchoring energy and bulk elastic energy within the confined chevron layer geometry of C1 and C2, it is possible to achieve a zigzag free C1 state by low azimuthal anchoring alignment with a low pretilt angle. The critical azimuthal anchoring coefficient for defect free C1 state is calculated. Its relationship with elastic constant, chevron angle as well as surface topography effect are also discussed. Second, using $5^{\circ}$ oblique SiO deposition alignment method a defect free, large memory angle, high contrast ratio and bistable C1 SSFLC display, which has potential for electronic paper applications has also been developed. The electrooptical properties and bistability of this device have been investigated. Various aspects of defect control are also discussed.

• 한국결정성장학회지
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• 제8권2호
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• pp.269-277
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• 1998

수소화된 비정질규소 박막의 결정화 방법은 물질의 질과 후속으로 제작되는 성능을 결정한다. 본 논문은 다양한 기판위에 성장된 비정질규소 박막의 결정화 특성조사와 고용체 형성 금속 박막의 유.무에 따른 결정화 효과를 분석하였다. 다양한 기판조사로부터 Mo 기판이 비정질규소 박막을 성장하기위해 선택되었다. 고용체 형성 금속을 사용하지않은 경우 $1100^{\circ}C$ 열처리후에 결정립의 크기가 $0.8{\mu}m$에 달하는 다결정을 얻었다. 결정화 온도를 줄이기 위해 고용체 형성 금속인 Au, Al, Ag등을 사용하였다. 금속 Au를 사용하여 $700^{\circ}C$ 열처리 후에 결정입경 크기가 $10{\mu}m$ 이상이며 (111) 면 우선배향 특성을 갖는 다결정규소 박막이 달성되었다. 광전소자 응용을 위하여 규소박막과 고용체를 형성하는 금속종류, 금속두께 등의 결정화 영향을 조사하였다.

• 전기전자학회논문지
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• 제18권2호
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• pp.214-219
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• 2014

본 논문에서는 실리콘 카바이드(silicon carbide)를 기반으로 한 tilt-implanted trench Schottky diode(TITSD)를 제안한다. 4H-SiC 트랜치 쇼트키 다이오드(trench Schottky diode)에 형성되는 트랜치 측면에 경사 이온주입(tilt-implantation)을 하여 소자가 역저지 상태(reverse blocking mode)로 동작 시 trench insulator가 모든 퍼텐셜(potential)을 포함하는 구조를 제안하고, 그 특성을 시뮬레이션을 통해 확인하였다. TITSD는 트랜치의 측면(sidewall)에 nitrogen을 $1{\times}10^{19}cm^{-3}$ 으로 도밍(doping) 하여 항복전압(breakdown voltage) 특성도 경사 이온주입을 하지 않았을 때와 같게 유지하면서 trench oxide insulator가 모든 퍼텐셜을 포함하도록 함으로써 termination area를 감소시켰다. 트랜치 깊이(trench depth)를 $11{\mu}m$로 깊게 하고 최적화된 폭(width)을 선택함으로써 2750V의 항복전압을 얻었고, 동급의 항복전압을 가진 가드링(guard ring) 구조보다 termination area를 38.7% 줄일 수 있다. 이에 대한 전기적 특성은 synopsys사의 TCAD simulation을 사용하여 분석하였으며, 그 결과를 기존의 구조와 비교하였다.

• Composites Research
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• 제35권1호
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• pp.23-30
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• 2022

폴리카보실란은 탄화규소 섬유 방사와 세라믹 제조를 위해 필요한 중요한 전구체이며, 이 전구체는 제조방법 및 공정에 따라 고내열성 및 내산화성 및 연속적인 탄화규소 섬유 생산 능력이 달라진다. 탄화규소 섬유는 폴리카보실란의 합성, 정제 및 분자구조제어기술, 그리고 이를 이용한 용융방사 및 안정화, 열처리 공정을 통해 제조된다. 본 논문에서는 폴리카보실란 전구체를 다양한 용매처리를 통하여 전구체 내에 존재하는 미반응물 및 저분자량의 정제효과를 파악하였으며, 또한 다양한 온도에서의 열처리에 따른 폴리카보실란 전구체의 중합 및 네트워크 재배열에 의한 변화에 대해 열적 분석을 실시하였다. 특히, 폴리카보실란 전구체의 유변물성 특성을 통해 용매처리 및 열처리에 따른 복합점도 및 구조적 배열의 변화를 분석하였다.