• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.4
• /
• pp.255-261
• /
• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.51-54
• /
• 2000

In this paper, $Ba_{0.5}$Sr$_{0.5}$TiO$_3$ thin films were prepared on Pt/Ti/SiO$_2$/Si substrate by RF magnetron sputtering method. We investigated effect of deposition conditions (especially RF input power) on structural properties of BST thin films. Deposit conditions of BST films were set working gas ratio, Ar:O$_2$= 70 : 30, working pressure 10mTorr, and RF input power 25W, 50W, 75W and 100W. Post-annealing using rapid thermal annealing(RTA) performed at 45$0^{\circ}C$, 55$0^{\circ}C$, $650^{\circ}C$, and 75$0^{\circ}C$ in oxigen ambient for 60 sec, respectively. The structural properties of BST films on Pt/Ti/SiO$_2$/Si substrate analysed by X-ray diffraction(XRD).).).

• Journal of Power Electronics
• /
• v.19 no.4
• /
• pp.1054-1067
• /
• 2019

This paper systematically investigates the influence of device parameters spread on the current distribution of paralleled silicon carbide (SiC) MOSFETs. First, a variation coefficient is introduced and used as the evaluating norm for the parameters spread. Then a sample of 30 SiC MOSFET devices from the same batch of a well-known company is selected and tested under the same conditions as those on datasheet. It is found that there is big difference among parameters spread. Furthermore, comprehensive theoretical and simulation analyses are carried out to study the sensitivity of the current imbalance to variations of the device parameters. Based on the concept of the control variable method, the influence of each device parameter on the steady-state and transient current distributions of paralleled SiC MOSFETs are verified separately by experiments. Finally, some screening suggestions of devices or chips before parallel-connection are provided in terms of different applications and different driver configurations.

• Journal of IKEEE
• /
• v.25 no.2
• /
• pp.371-375
• /
• 2021

In this paper, a SiC-based LIGBT structure that can be used at high voltage and high temperature is presented. In order to improve the low current characteristic, a dual-emitter symmetrical around the gate is inserted. In order to verify the characteristics of the proposed device, simulation and design were conducted using Sentaurus TCAD simulation, and a comparative study was conducted with a general LIGBT. In addition, splitting was performed by designating a variable for the length of the N-drift region in order to verify the electrical characteristics of the minority carriers. As a result of the simulation it was confirmed that the proposed dual-emitter structure flows a higher current at the same voltage than the conventional LIGBT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.71-74
• /
• 1996

Ta$_2$O$_{5}$ film ale recognized as promising capacitor dielectric for future DRAM\`s. The electrical properties of Ta$_2$O$_{5}$films greatly depend on the heating condition. In the practical fabrication process, several annealing process, such as the annealing of Al in H$_2$(about 40$0^{\circ}C$) and reflow of BPSG (borophosphosilicate glass) film in $N_2$(about 80$0^{\circ}C$), exist after deposition of Ta$_2$O$_{5}$ film. In this paper, we describe the temperature effect on the electrical properties of W/Ta$_2$O$_{5}$/Si structure. The thin film of Ta$_2$O$_{5}$ and tungsten have been deposited on p-si(100) wafer using the sputtering system. The heating temperature was varied from 500 to 90$0^{\circ}C$ in $N_2$for 30min and The degree of temperature is 100\`C. In a log(J/E$^2$) Vs 1/E plot of typical I-V data, we find a linear relationship for the temperature of 500, $600^{\circ}C$ and as deposition. This could indicate Fowler-Nordheim tunneling as the dominant mode of current transports. However, we can not find a linear relationship for the temperature above $700^{\circ}C$. This could not indicate Fowler-Nordheim tunneling as the dominant mode of current transport. The high frequency (1MHz) capacitance-voltage (C-V) of W/Ta$_2$O$_{5}$/Si Capacitor were investigated on the basis of shift in the threshold voltage and dielectric constant. The magnitude of the threshold voltage and dielectric constant depends on the heating temperature, and increases with heating temperature.temperature.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.284-292
• /
• 2020

SiC-based devices perform well in high-voltage environments of more than 1200V compared to silicon devices, and are particularly stable at very high temperatures. Therefore, 1700V UMOSFET has been actively researched and developed for the use of electric power systems such as electric vehicles and aircrafts. In this paper, we analysed thermal variations of critical variables (breakdown voltage (BV), on-resistance (R_on), threshold voltage (v_th), and transconductance (g_m)) for the three type 1700V UMOSFETs-Conventional UMOSFET (C-UMOSFET), Source Trench UMOSFET (ST-UMOSFET), and Local Floating Superjunction UMOSFET (LFS-UMOSFET). All three devices showed BV increase, R_on increase, v_th decrease, and g_m decrease with increasing temperature. However, there are differences in BV, R_on, v_th, g_m according to the structural differences of the three devices, and the degree and cause of the analysis were compared. All results were simulated using sentaurus TCAD.

• KIEE International Transactions on Electrophysics and Applications
• /
• v.3C no.2
• /
• pp.55-58
• /
• 2003

This paper examines the electrical characteristic of single oxide layer due to various diffusion conditions, substrate orientations, substrate resistivity and gas atmosphere in a diffusion furnace. The oxide quality was examined through the capacitance-voltage characteristic due to the annealing time after oxidation process, and the capacitance-voltage characteristics of the single oxide layer by will be described via semiconductor device simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.570-573
• /
• 2001

In this paper, GaN films have been grown on SiO$_2$/Si(100) substrates by RF magnetron sputtering. To obtain high quality GaN films, we used ZnO buffer layer and modified the process conditions. The charateristics of GaN films on RF power, substrate temperature and Ar/N$_2$gas ratio have been investigated by Auger electron spectroscopy and X-ray diffraction analysis. At RF power 150W, substrate temperature 500 $^{\circ}C$ and Ar/N$_2$=1:2 gas ratio, we could grow high quality GaN films. Through the atomic force microscope and photoluminescence analysises, it was observed that the crystallization of GaN films was improved with increasing annealing temperature and the optimal crystallization of GaN films was found at 1100 $^{\circ}C$ annealing temperature.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.65-66
• /
• 2000

Various fluoride films on a glass substrate were prepared and characterized to provide a seed layer for crystalline Si film growth. The XRD analysis on $CaF_2/glass$ illustrated (220) preferential orientation and showed lattice mismatch less than 5 % with Si. We achieved a fluoride film with breakdown electric field of 1.27 MV/cm, leakage current density about $10^{-6}$ $A/cm^2$, and relative dielectric constant less than 5.6. This paper demonstrates microcrystalline silicon $({\mu}c-Si)$ film growth by using a $CaF_2/glass$ substrate. The ${\mu}c-Si$ films exhibited crystallization in (111) and (220) planes, grain size of $700\;{\AA}$, crystalline volume fraction over 65 %, dark- and photo-conductivity ratio of 124, activation energy of 0.49 eV, and dark conductivity less than $4{\times}10^{-7}$ S/cm.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.50 no.5
• /
• pp.249-252
• /
• 2001

The paper represents the design and fabrication of an electrostatic micro actuator with $p^+$,/TEX> Si cantilevers. The micro actuator consists of a plate suspended by four $p^+$,/TEX> silicon cantilevers and an electrode on a glass substrate. The $p^+$,/TEX> Si structure is fabricated by the boron diffusion process and the anisotropic wet etch process. The cantilevers of the micro actuator curl down because of the residual stress gradient in $p^+$,/TEX> silicon. When the electrostatic forec is applied to the $p^+$,/TEX> cantilevers, the vertical displacement of the plate can be achieved. The deflection of the cantilever due to the residual stress gradient and the vertical displacement by electrostatic force were calculated. The displacement of the plate was measured with a laser displacement meter for various input voltages and frequencies. The feasibility of the proposed micro actuator for the applications to optical pickup devices or optical communication devices was confirmed by the experiments.