Influence of Device Parameters Spread on Current Distribution of Paralleled Silicon Carbide MOSFETs

Abstract

This paper systematically investigates the influence of device parameters spread on the current distribution of paralleled silicon carbide (SiC) MOSFETs. First, a variation coefficient is introduced and used as the evaluating norm for the parameters spread. Then a sample of 30 SiC MOSFET devices from the same batch of a well-known company is selected and tested under the same conditions as those on datasheet. It is found that there is big difference among parameters spread. Furthermore, comprehensive theoretical and simulation analyses are carried out to study the sensitivity of the current imbalance to variations of the device parameters. Based on the concept of the control variable method, the influence of each device parameter on the steady-state and transient current distributions of paralleled SiC MOSFETs are verified separately by experiments. Finally, some screening suggestions of devices or chips before parallel-connection are provided in terms of different applications and different driver configurations.

I. INTRODUCTION

Silicon carbide (SiC) MOSFETs have excellent blocking voltage capability, high switching frequency, low losses, and high thermal conductivity [1], [2]. Currently, with limitations of the current rating of a single chip or device [3], power modules with paralleled multi-chips or the parallel connection of several discrete SiC MOSFET devices in a TO-package are commonly being developed to achieve high current capability [4]. However, there is a current imbalance among paralleled units (chips or devices) if their parameters or the parasitic parameters of their corresponding circuits are not perfectly matched. This may result in a difference in the power losses by the individual units in the form of conduction and switching losses, which can result in further thermal dissymmetry. In addition, a difference of the di/dt among all of the paralleled switches can lead to mismatches of the current overshoot during turn-on and voltage overshoot during turn-off. These overshoots may push devices out of their safe operating area (SOA), or even cause device destruction. Current de-rating, which is a common approach adopted to safeguard devices from destruction due to current imbalance, has the disadvantage of inhibiting the full utilization of the overall current capacity of paralleled chips or devices.

Recently, some researchers have studied current imbalance in terms of two main aspects, circuit parasitic parameters and devices parameters. With regards to circuit parasitic parameters mismatches, the effects of parasitic inductance mismatches on paralleled modules was studied in [5]. Meanwhile, the authors of [6] conducted similar studies on discrete devices and the authors of [7] extended this study to the multi-chips in power modules. An optimized driver circuit [5], auxiliary source connections [7] and a symmetrical power module structure [8] were proposed to improve transient current sharing in paralleled units. Even though it is possible to realize a sufficiently symmetrical circuit layout with almost perfectly matched parameters, a mismatch in the inherent device parameters can still lead to an uneven current distribution. Therefore, uniformity of the device parameters is a required precondition for adopting circuit layout symmetry as a means of realizing equal current sharing.

Although the fluctuations of device parameters are often limited by strict fabrication processes for commercial semiconductors, there is still a certain degree of inconsistency in device parameters. This is especially true for emerging SiC devices, where the spread of the device parameters is distinct. The main cause of this inconsistency may be the relatively immature manufacturing process control which has been reported in [9]-[11]. In addition, the higher the number of paralleled devices, with the aim of achieving a higher current capability, the higher the risks of SiC MOSFETs bearing static and dynamic over-currents. The large spread of the pinch-off voltage and reverse breakdown gate voltage of SiC JFET devices have been reported in [4], [12], [13]. In these studies, an individual gate driver circuit is used to solve this problem. Similar researches for SiC MOSFET devices have also been mentioned in a number of published studies [14]-[18]. The spread of on-resistance and threshold voltage, and their influences on the current distribution among paralleled SiC MOSFET devices, have been discussed. A de-rating calculation method was presented in [18] to avoid thermal overstress for paralleled SiC MOSFET devices. However, a systematic and comprehensive analysis of all the device parameters has not been reported yet. This is especially true for parasitic capacitance and trans-conductance. Moreover, the influence of the spread of device parameters on current distribution under different gate driver configurations and temperatures also needs to be discussed. These analyses are usually very important for gate driver design and form the basis for device screening methods.

This paper takes full consideration of device parameters spread and their influence on current distribution. In section II, 30 SiC MOSFET devices from the same batch are tested under the same condition used in the datasheet. The spread of the device parameters is presented using the coefficient of variation. The cause of the differences among the spreads of three parasitic capacitances are discussed. In section III, the influences of on-resistance, threshold voltage and trans-conductance on steady-state and transient current distributions are theoretically studied. The sensitivity of capacitance variations to current imbalance is quantitatively calculated by simulation software. In section IV, several pairs of different devices are selected from the samples for switching operation experiments in parallel connection. The obtained experimental results validate the theoretical and simulation analyses of the influence of all the parameters. The junction temperature variation at the maximum difference of the main device parameters is discussed in section V. Several valuable screening guidelines are provided in section VI. Some conclusions are given in section VII.

II. DEVICE PARAMETERS SPREAD

Generally, the current distribution of paralleled devices is a result of multiple factors including the device and circuit parameters. The device parameters include the on-resistance, threshold voltage, trans-conductance, internal gate resistance and parasitic capacitances. The spreads of the different device parameters are not the same. Thus, a norm needs to be defined to quantitatively assess the spread of the device parameters.

In experimental statistics, there are several norms, such as the range, variance, standard deviation and coefficient of variation, that describe the spread of data. Since the range only considers the two extrema, and cannot reflect the concentration and spread of a group of data, it is not widely used. The unit of variance is the square of the original data’s unit, which often makes its real meaning difficult to understand [19]. Although the unit of the standard deviation is the same as that of the original data, it is not suitable for comparing the spread of different parameters in a sample. The coefficient of the variation δ_N is the ratio of the standard deviations σ_N to the mean μ_N. It is unit-less and usually expressed as a percentage [20]. It is a more suitable option for the description of the spread of parameters. Therefore, this paper uses δ_N to evaluate the spread of the device parameters.

\(\delta_{\mathrm{N}}=\frac{\sigma_{\mathrm{N}}}{\mu_{\mathrm{N}}} \times 100 \%\)       (1)

where N is the sample space, which is set to N=30 in this paper.

A. On-Resistance

In this paper, 30 SiC MOSFETs are tested at an ambient temperature of 25℃ and a gate voltage of +20V. The on-resistance spread of different devices with different drain currents is shown in Fig. 1. The devices with the largest and smallest on-resistances in the entire range of the drain current are No.6 and No.19, respectively. Moreover, in the 20A range of the drain currents, the δ₃₀ of the on-resistance varies from 4% to 5.37% due to inconsistencies of the output characteristics of the different devices. The on-resistance of a power MOSFET is mainly composed of the channel resistance and the drift region resistance. These are affected by the device structure and fabrication technology such as the channel length, the cell width, the drift region thickness, etc. [21]. Therefore, it is difficult to keep them uniform even for the same batch of products from the same manufacturer.

Fig. 1. R_DS-I_D curve of SiC MOSFET devices.

B. Internal Gate Resistance

The internal gate resistance R_{G_int}, mainly depends on the film thickness and resistivity of the gate electrode material [22]. The spread of R_{G_int}, for the 30 SiC MOSFET devices selected in this paper is shown in Fig. 2. Although the datasheet gives a typical value of 4.6Ω for R_{G_int}, the actual value varies from device to device. Among these devices, the largest and smallest R_{G_int}, are 4.48Ω and 3.04Ω, which correspond to device No.21 and No.7, respectively. These are lower than the datasheet specifications. The mean of R_{G_int} is 3.79Ω, its standard deviation is 0.463Ω, and the coefficient of variation is 12.2%, which indicate that R_{G_int} has a large spread. This may be caused by the tolerance of the chip size and sheet thickness.

Fig. 2. Spread of internal gate resistance.

C. Parasitic Capacitances

MOSFET internal parasitic capacitances include gate-source capacitance C_GS, gate-drain capacitance (or reverse transfer capacitance) C_GD and drain-source capacitance C_DS. Generally, C_GS is assumed to be constant with the voltage [23]. As shown in Fig. 3(a), although C_GS has little variation with V_DS below the value of 20V, it is not more than 8% of the steady-state value. In addition, whether in turn-on or turn-off transient stage, the V_DS value is relatively high and much higher than the 20V during the current rising or falling stage. In addition, the variation of C_GS with V_DS does not exceed 1%. As shown in Fig. 4, the spread of C_GS, which may be caused by the tolerance control of the oxide thickness and cell width also remains constant under the varying of V_DS. However, C_GD and C_DS both dramatically decrease with an increase of V_DS as shown in Fig. 3(b), since both are constituted by the depletion layer capacitance, which depends on the width of the depletion layer and the junction area of the drain region of the body [24]. In addition to the inverse variation with V_DS, there is a large change of C_GD around the Miller platform voltage 12.5V. This is because the doping concentrations in the JFET region and the drift region are different, which results in the two depletion layers having different capacitances [23], [25]. Thus, it is significantly different from the rate of decrease at less and more than 12.5V. This abrupt change of C_GD around 12.5V results in large spread as shown in Fig. 4.

Fig. 3. C-V curves of a SiC MOSFET. (a) C_GS -V_DS; (b) C_DS-V_DS and C_GD -V_DS.

Fig. 4. Coefficient of the variation of parasitic capacitances.

D. Transfer Characteristics

The transfer characteristics of a MOSFET are crucial for the transient current distribution in parallel-connection applications [26]. In this paper, the transfer curves of 30 SiC MOSFET devices are measured under the same conditions of V_DS = 20V and T_C = 25℃. It can be seen from Fig. 5 [27] that there is still a large spread of the transfer curves even though the devices are drawn from the same batch.

Fig. 5. Transfer curves of SiC MOSFET devices [27].

During the current rising or falling stage, the MOSFETs are operating in the saturation region and the drain current is expressed by (2) [28]. The transfer characteristics can also be regarded as a function of the threshold voltage V_th and the trans-conductance g_fs.

\(i_{\mathrm{D}}=g_{\mathrm{fs}}\left(V_{\mathrm{GS}}-V_{\mathrm{th}}\right)\)       (2)

\(V_{\mathrm{th}}=\frac{\sqrt{4 \varepsilon_{\mathrm{s}} k T N_{\mathrm{A}} \ln \left(N_{\mathrm{A}} / n_{i}\right)}}{C_{\mathrm{OX}}}+\frac{2 k T}{q} \ln \left(\frac{N_{\mathrm{A}}}{n_{i}}\right)-\frac{Q_{\mathrm{OX}}}{C_{\mathrm{OX}}}\)       (3)

\(g_{\mathrm{fs}}=\frac{\mu_{\mathrm{ni}} C_{\mathrm{ox}} Z}{L_{\mathrm{CH}}}\left(V_{\mathrm{GS}}-V_{\mathrm{th}}\right)\)       (4)

where ε_s, k, q, T, N_A, ni, μ_ni, COX, Z and L_CH are the material dielectric constant, Boltzmann constant, electronic charge amount, Kelvin temperature, acceptor impurity concentration, intrinsic carrier concentration, channel electron mobility, gate oxide capacitor, cell length perpendicular to the cross section and channel length, respectively. Q_OX is the total effective oxide charge, including the moving ionic charge, oxide trap charge, fixed oxide charge and interfacial charge.

Even though current SiC material technology has been greatly improved, it is still not as mature as silicon technology, especially in terms of controlling defects. Slight inconsistencies in these defects may bring about differences in the interface and oxide layer quality resulting in differences in Q_OX in the oxide layer. According to (3), the Q_OX differences can lead to a large spread of V_th. In addition, the C_OX difference, caused by production processes such as inconsistent doping concentrations and thickness of the gate oxide layer, can also lead to inconsistencies in V_th [29]. On the other hand, as shown in (4), g_fs is also affected by the differences in Cox, V_GS, V_th and other fabrication parameters [25]. The dispersion of V_th also affects that of g_fs. In addition, g_fs is variable with the current. Therefore, g_fsmax is taken as an example to present the spread of g_fs. As shown in Fig. 6, the spread of V_th is larger than that of g_fsmax. The variation coefficients δ₃₀ of V_th and g_fsmax for the 30 devices selected in this paper are 13.8% and 3.73%, respectively.

Fig. 6. Spread of threshold voltage and trans-conductance.

In summary, for the 30 SiC MOSFETs selected in this paper, the δ₃₀ of the threshold voltage and the gate resistance are larger with both exceeding 10%. In contrast, the δ₃₀ of the on-resistance and trans-conductance are relatively small. Although the δ₃₀ of C_GD changes sharply around 12.5V, it decreases with an increasing V_DS. For a V_DS above 400V, among the three capacitances, the δ₃₀ of C_GS is the largest followed by that of C_GD, while C_DS has the smallest δ₃₀. In this case, the value of δ₃₀ is less than 6% for all of them.

III. INFLUENCE OF DEVICE PARAMETERS ON CURRENT DISTRIBUTION

The above analysis shows that the device parameters still have a large spread, even though the tested products were drawn from the same batch and produced by the same manufacturer. Thus, this section focuses on the impact of device parameters mismatch on steady-state and transient current distributions.

A. On-Resistance

If it is assumed that the same gate driver circuit is used to supply the gate pulse for both of the paralleled devices, there is no disparity in the gate bias voltages. When all of the paralleled devices are fully on, a steady-state equivalent circuit of paralleled devices is shown in Fig. 7. Assume that the circuit layout is symmetrical, all of the stray resistances are considered to be equal and can be uniformly expressed as R_stray. The j^th branch current I_Dj can be expressed by (5).

\(I_{\mathrm{D} j}=\frac{I_{\mathrm{D}}}{\left(R_{\mathrm{DS}(\mathrm{on}) j}+R_{\text {stray }}\right) \sum_{i=1}^{N} \frac{1}{R_{\mathrm{DS}(\mathrm{on}) i}+R_{\text {stray }}}} \ i, j=1,2, \cdots, N\)       (5)

where R_{DS (on)i} and R_{DS (on)j} are devices’ on-resistances for the i^th and j^th branches, respectively. ID is the total current. N is the number of paralleled devices.

Fig. 7. Steady-state equivalent circuit of paralleling devices.

The steady-state current imbalance m can be defined as:

\(m=\frac{\left|I_{\mathrm{Dmax}}-I_{\mathrm{Dmin}}\right|}{I_{\mathrm{D}} / N}\)       (6)

where I_Dmax and I_Dmin are the maximum and minimum of the steady state current of paralleled devices.

Substituting (5) into (6) yields the steady-state current imbalance of N devices in parallel as:

\(m=\frac{\left|R_{\mathrm{DS}(\mathrm{on}) \mathrm{max}}-R_{\mathrm{DS}(\mathrm{on}) \min }\right|}{\frac{1}{N} \sum_{j=1}^{N} \frac{\left(R_{\mathrm{DS}(\mathrm{on}) \mathrm{max}}+R_{\mathrm{stray}}\right)\left(R_{\mathrm{DS}(\mathrm{on}) \mathrm{min}}+R_{\mathrm{stray}}\right)}{R_{\mathrm{DS}(\mathrm{on}) j}+R_{\mathrm{strayj}}}}\)       (7)

According to (7), it can be observed that the steady-state current distribution depends on the differences among the on-resistances provided that the layout is symmetrical. Although increasing the stray resistance of the paralleled branches can reduce the imbalance of the steady-state current, this is undesirable since it introduces extra power loss.

B. Internal Gate Resistance and Parasitic Capacitances

The rising or falling speed of the gate voltage mainly depends on the rate of charging or discharging of the device input capacitance. The turn-on and turn-off delay time is a function of the input parasitic capacitance and the gate resistance, which can be expressed as:

\(t_{\mathrm{don}}=\left(R_{\mathrm{G}_{-} \mathrm{int}}+R_{\mathrm{G}_{-} \mathrm{ext}}\right)\left[C_{\mathrm{GS}}+C_{\mathrm{GD}}\left(V_{\mathrm{DS}_{-} \mathrm{off}}\right)\right] \ln \frac{V_{\mathrm{GH}}}{V_{\mathrm{GH}}-V_{\mathrm{EE}}-V_{\mathrm{th}}}\)       (8)

\(t_{\mathrm{doff}}=\left(R_{\mathrm{G}_{-} \mathrm{int}}+R_{\mathrm{G}_{-} \mathrm{ext}}\right)\left[C_{\mathrm{GS}}+C_{\mathrm{GD}}\left(V_{\mathrm{DS}_{-} \mathrm{on}}\right)\right] \ln \frac{V_{\mathrm{GH}}+V_{\mathrm{EE}}}{V_{\mathrm{GP}}+V_{\mathrm{EE}}}\)       (9)

where R_{G_int} and R_{G_ext} are internal and external gate resistances, and V_GH and -V_EE are the positive and negative bias gate voltages. V_GP is the gate Miller platform voltage.

During turn-on or turn-off transients, the current distribution depends on the difference among switching delay times and on the difference among current changing rates. Furthermore, the current rate is influenced by many factors including the common-source parasitic inductance, threshold voltage, trans-conductance, etc. It is difficult to deduce the exact analytical formula that relates the switching delay time to the current sharing. Therefore, in this paper, a simulation model consisting of a parallel combination of two devices is built in LTSPICE and used to study the current distribution by deliberately changing the C_GS and R_{G_ext} values.

In order to quantitatively describe the transient current distribution of paralleled devices, an evaluation indicator should be defined. Usually, the transient current imbalance is defined based on the difference in the peak values of the transient currents [30]-[32]. However, there is no peak value for the turn-off transient current if the difference in the turn-off delay time is not too large. Therefore, in this paper, the ratio α of the maximum absolute value of transient current difference to the base value is used to define transient current imbalance.

\(\alpha=\frac{\left|\Delta i_{\mathrm{D}}\right|_{\max }}{I_{\mathrm{B}}} \times 100 \%\)       (10)

In (10), |Δi_D|_max represents the maximum absolute value of the transient current difference. This is the largest instantaneous current unbalance over the entire transient period. I_B is the base value and it represents the current value at the first turn-off.

In Fig. 8, both the turn-on and turn-off current imbalance increase with an increasing difference of C_GS under the same gate resistance. The slope of the current imbalance also increases with the gate resistance. This means that the sensitivity of the influence of the C_GS mismatch on the current imbalance increases with the gate resistance. In addition, if the difference of C_GS is held constant, the current imbalance also increases with an increasing gate resistance due to the consequent increase in the difference of the switching delay time.

Fig. 8. Current imbalance under different C_GS and R_{G_ext}. (a) Turn-on current imbalance. (b) Turn-off current imbalance.

C. Threshold Voltage and Trans-Conductance

During the transient process, when the gate bias voltage exceeds V_th, the current starts to increase. According to (2), the drain current of the saturated region mainly depends on the gate bias voltage, V_th and g_fs. Assuming that a single driver is adopted for the paralleled SiC MOSFETs so that their gate bias voltages are the same, the maximum current difference can be derived from (2) and expressed as (11).

\(\Delta i_{\mathrm{Dmax}}=\frac{\Delta g_{\mathrm{fs}} i_{\mathrm{D}}+\Delta g_{\mathrm{fs}} \sum_{j=1}^{N} g_{\mathrm{fs} j} V_{\mathrm{th} j}}{\sum_{j=1}^{N} g_{\mathrm{fs} j}}+g_{\mathrm{fsmin}} V_{\mathrm{thmax}}-g_{\mathrm{fsmax}} V_{\mathrm{thmin}} \)       (11)

where Δi_Dmax is the maximum transient current difference. g_fsmax and g_fsmin are the maximum and minimum trans-conductance, respectively. V_thmax and V_thmin are the maximum and minimum threshold voltages, while Δg_fs is the difference of the trans-conductance. i_D is the total transient current.

Similarly, taking two devices as an example, N is equal to two. Assuming that the difference between the trans-conductance values is small enough that it can be approximated that g_fs1= g_fs2= g_fs, (11) can be simplified to:

\(\frac{i_{\mathrm{D} 1}-i_{\mathrm{D} 2}}{V_{\mathrm{th} 1}-V_{\mathrm{th} 2}}=\frac{\Delta i_{\mathrm{D}}}{\Delta V_{\mathrm{th}}}=-\frac{g_{\mathrm{fs}}}{2}<0\)       (12)

When the V_th variation is very small, it can be further approximated that V_th1=V_th2. In addition, (11) can be simplified to:

\(\frac{i_{\mathrm{D} 1}-i_{\mathrm{D} 2}}{g_{\mathrm{fs} 1}-g_{\mathrm{fs} 2}}=\frac{\Delta i_{\mathrm{D}}}{\Delta g_{\mathrm{fs}}}=\frac{i_{\mathrm{DT}}}{g_{\mathrm{fs} 1}+g_{\mathrm{fs} 2}}>0\)       (13)

For paralleled devices, the greater the difference of either the V_th or g_fs values, the more severe the current imbalance becomes. Moreover, current imbalance increases with the current levels. According to (12), the derivative of the current imbalance with respect to the difference of V_th is negative. This indicates that the device with the largest V_th carries the least drain current during switching transients. Conversely, as presented in (13), the derivative of the current imbalance with respect to the difference of g_fs is positive. Hence, the device with the largest g_fs conducts most drain current during switching transients. Therefore, the two parameters have offsetting or supporting impacts on current sharing, which depend on the relative values of V_th and g_fs of the two devices.

IV. EXPERIMENTAL ANALYSIS

A. Experiment Platform

As shown in Fig. 9, a double pulse test platform with two-devices connected in parallel is set up. The test platform includes a digital signal processor, DC bus-bar, driver circuit, charging and discharging loop and auxiliary power supply. In order to avoid the influence of circuit parasitic parameters’ mismatch, the circuit layout is designed to be as symmetrical as possible.

Fig. 9. Double pulse test platform for two-paralleled devices.

Typically, the rising and falling times of the current and voltage for SiC MOSFETs are in the range of 20ns-100ns. To ensure the reliability of measurement results in the actual test, a bandwidth margin of 3-5 times is generally needed, which is at least 52.5MHz-87.5MHz as calculated by (14) [33].

\(\mathrm{BW}=0.35 / \min \left[t_{\mathrm{r}}, t_{\mathrm{f}}\right]\)       (14)

The selected measuring probe fully meets the bandwidth requirements of the signal under test. In addition, the external gate resistances are separately connected to each of the two devices and a resistance value of 37.5Ω is used in all of the experiments in this paper unless otherwise specified.

B. On-resistance R_DS

In this paper, two devices, identified as No. 4 and No. 23, with a large difference in the on-resistance values and small differences of other parameters’ values, are selected. The on-resistances of devices No. 4 and No. 23 at 20A are 77.32 mΩ and 86.77 mΩ, respectively. Fig. 10 shows that No. 23 conducts less of the steady-state current due to its higher on-resistance. Although the steady-state current imbalance m between No. 4 and No. 23 is 11.1% and remains constant, the difference in the actual steady-state current increases with the load current as a result of the gradual increase in the average current, as depicted by (6). The turn-on transient current imbalance is only 3.8% despite the large difference in on-resistance between the two devices. However, the turn-off transient current imbalance reaches 16.8%. This demonstrates that the switching transient current distribution is not sensitive to the spread of the on-resistance. However, the on-resistance indirectly affects the turn-off current distribution by influencing the initial current difference just before turn-off.

Fig. 10. Current distribution of paralleled devices No.4 and No.23.

C. Gate-source Capacitance C_GS

There are many factors that affect the transient current distribution among paralleled units. It is hard to select proper experimental sample from the 30 devices since the spread of V_th is relatively large. Thus, it is difficult to control each of the variables separately. In this paper, devices No.24 and No.27, with almost equal parameter values, are used to study the influence of differences in the parasitic capacitances or internal gate resistance between devices by the insertion of a capacitor or a resistor. The most important parameters of devices No.24 and No.27 are shown in Table I. Fig. 11 shows that both the steady-state and transient current imbalances are very small, where a value of 0.5% is calculated for the steady-state current and values of 4.3% and 3.4% are calculated for the turn-on and turn-off transient currents, respectively. This indicates that this set of devices can be selected as a reference.

TABLE I PARAMETERS OF DEVICES NO.24 AND NO.27

Fig. 11. Current distribution of paralleled devices No.24 and No.27.

Among all of the devices, the difference of C_GS between devices No. 25 and No. 30 is the largest and reaches 200pF under a bias voltage of 500V. To avoid the superposition effect of the other parameters, devices No.24 and No.27 are selected. Then, 110pF and 220pF ceramic capacitors are connected in parallel across the gate-source terminal of device No.24. As shown in Fig. 12, the turn-on and turn-off transients of device No.24 is slower than that of device No.27. Therefore, device No.27 carries more current during turn-on transients, and less current during turn-off transients. When ΔC_GS is 110pF, the turn-on and turn-off transient current imbalances are 10.4% and 10.3% as shown in Fig. 12 (a). When ΔC_GS is 220pF, the turn-on and turn-off transient current imbalances are 14.3% and 15.9% as shown in Fig. 12 (b). This means that the spread of C_GS and its effect on the transient current distribution under a 37.5Ω external gate resistance cannot be ignored. In addition, similar to the above simulation results, the effect of a C_GS mismatch on the transient current under the parallel configuration of SiC MOSFETs is also related to the gate resistance. As shown in Fig. 12 (c), the turn-on and turn-off transient current imbalances are 8.3% and 10.1% when the external gate resistance is 10Ω. This shows that the effect of a C_GS mismatch on the transient current of paralleled MOSFETs can be ignored under a small external gate resistance. As for the steady-state current distribution, there is a negligible effect of C_GS.

Fig. 12. Current distribution under different C_GS and R_{G_ext}. (a) C_GS=110pF, R_{G_ext}=37.5Ω. (b) C_GS=220pF, R_{G_ext}=37.5Ω. (c) C_GS=220pF, R_{G_ext}=10Ω.

Generally, there are two concepts for the gate driver circuit, the fully decoupling driver configurations (FDDC) and the partly decoupling driver configurations (PDDC) as shown in Fig. 13. All of the experiments described above are conducted under the FDDC. Thus, the external gate resistances are separately connected. According to the above analysis, the sensitivity of the transient current imbalance to ΔC_GS also depends on the decoupling gate resistance due to the switching delay difference. To fairly compare two configurations, R_{G_ext1}=R_{G_ext2}=2_{RG_ext} is used to achieve a comparable switching speed. As can be seen in Fig. 14, the transient current imbalance for the turn-on and turn-off are 7.38% and 8.65% at rising time and falling time of 28.8ns and 26.1ns. This is similar to the FDDC with 29.6ns and 31.2ns in Fig. 12(b). In contrast, the PDDC, with a smaller decoupling gate resistance, can mitigate the transient current imbalance caused by the spread of C_GS.

Fig. 13. Two gate driver concepts.

Fig. 14. Current distribution with ΔC_GS=220pF under the PDDC.

D. Drain-source Capacitance C_DS

Under a clamped inductive load, the drain current rises first and then V_DS falls during the turn-on process. Then a reverse sequence of these events happens. Thus, V_DS is relatively high during the entire current rising and falling stage. This means that the spreads of C_DS and C_GD are relatively small due to the high drain-source voltage bias for the analysis of the transient current distribution. The maximum value of ΔC_DS for the 30 devices is 11 pF at 200V and 6 pF at 500V. Similarly, a ceramic capacitor is connected in parallel with device No.24 to mimic this difference. As shown in Fig. 15, the transient currents of devices No.24 and No.27 are almost the same under a ΔC_DS of 10pF. This means that the influence of the C_DS spread on the transient current distribution can be ignored. Furthermore, the C_DS mismatch has negligible effect on the steady-state current distribution. Thus, the C_DS screening may be neglected before paralleled application.

Fig. 15. Current distribution of paralleled devices No.24 and No.27 under ΔC_DS=10pF.

E. Gate-drain Capacitance C_GD

Similar to C_DS, the spread of C_GD is also small during the current rising and falling stages. The range for the 30 devices at 500V is less than 1pF. Limited by the capacitance range of the high-voltage ceramic capacitors, a ceramic capacitor of 3pF is connected in parallel with device No.24. As shown in Fig. 16, C_GD has little effect on the current rising and falling in comparison to C_GS due to its comparatively much smaller value. However, the displacement current caused by the fast rate of the change of V_DS flows through C_GD. Thus, there is obviously a current difference during the rising or falling stage of V_DS. The turn-on and turn-off current imbalances are 10% and 13.3%, respectively. Generally, both C_GD and ΔC_GD are small at a high bias voltage. In addition, the maximum difference of C_GD for the 30 samples measured in this paper is not more than 1pF. Thus, it can be regarded that the corresponding current imbalance does not exceed 10%. Moreover, similar to C_GS and C_DS, C_GD has little effect on the steady-state current distribution.

Fig. 16. Current distribution of paralleled devices No. 24 and No. 27 under ΔC_GD=3pF.

F. Internal gate resistance R_{G_int}

The static test results presented in the previous section show that the range of R_{G_int} for the 30 devices selected in this paper is 1.4Ω. In order to avoid too large a gate resistance, which can amplify the influence of the parasitic capacitance, the 1.4Ω difference of the resistance, under a 10Ω external gate resistance, is inserted to study the influence of R_{G_int} on current distribution in this paper. As shown in Fig. 17, the turn-on and turn-off transient current imbalances are 4.8% and 6.6%, respectively. In addition, the difference of R_{G_int} has almost no effect on the steady-state current distribution. Therefore, the spread in the R_{G_int} values may not be considered before the parallel connection of SiC MOSFET devices.

Fig. 17. Effect of R_{G_int} on the current distribution of paralleled devices.

G. Threshold Voltage V_th and Trans-conductance g_fs

For an experimental investigation of the influence of V_th and g_fs on transient current distribution, two pairs of devices from the 30 devices sample are selected in this paper. Devices No. 4 and No. 30 are uses as the first pair and No. 12 and No.19 are used as the second pair. There are several reasons behind this choice. First, it is not necessary to ensure the consistency of on-resistance due to its insignificant influence on transient current distribution. Second, the influence of the differences in the values of R_{G_int}, C_DS and C_GD is relatively small. Third, the spread of the parasitic capacitance C_GS is small, implying that its distribution is centralized. Thus, devices with satisfactory parameters can be directly selected from the sample. The parameters of the selected devices are shown in Table II. For the first pair, device No.12 has larger V_th and smaller g_fs values when compared to device No.19. For the second pair, device No.4 has larger values for both V_th and g_fs when compare to those of device No.30. As shown in Fig. 18, device No.19 turns on earlier and its drain current rises faster. This indicates that the effects of the threshold voltage mismatch and trans-conductance mismatch have a positive compensation effect, resulting in an increased current imbalance. The turn-on and turn-off transient current imbalances are 23.7% and 23.2%, respectively. However, for the second pair, Fig. 19 shows that the turn-on and turn-off transient current imbalances are 10.3% and 4.6%, respectively. This is because the offsetting impacts between V_th and g_fs make the turn-on and turn-off current distribution significantly better than those of the first pair. Thus, the overall effects of V_th and g_fs should be considered. Actually, the trans-conductance is a variable with drain current, which is difficult to screen with a single measured value. Transfer curves screening combined the threshold voltage and trans-conductance may be a better way to address this issue, which will be further developed in future research work.

TABLE II PARAMETERS COMPARISON OF DEVICES NO.12, NO.19, NO.4 AND NO.30

Fig. 18. Current distribution of paralleled devices No. 12 and No. 19.

Fig. 19. Current distribution of paralleled devices No. 4 and No. 30.

H. Influence of Junction Temperature on Current Distribution

The temperature dependency of the characteristic parameters of SiC MOSFET devices has been widely reported [34], [35]. The important parameters that are sensitive to temperature are the threshold voltage, on-resistance and trans-conductance. However, the spread of these parameters at different temperatures should be further discussed. The same samples mentioned above are tested in the range of 25℃-165℃. As shown in Fig. 20 [36], the overall variation of the on-resistance increases with an increasing junction temperature, while the spread of the threshold voltage and trans-conductance display a low sensitivity to junction temperature.

Fig. 20. Device parameters spread under various temperatures [36].

A set of devices, No. 6 and No. 28, is taken as an example to illustrate the influence of junction temperature on the current distribution of paralleled devices. As shown in Fig. 21, the steady-state current difference at 125℃ is larger than that at 25℃. This is because the on-resistances of devices No. 6 and No. 28 are 90mΩ and 83 mΩ at 25℃, whereas they are 157 mΩ and 135 mΩ at 125℃. As for the transient current distribution, the drain current of the same device increases with the junction temperature due to the negative temperature coefficient of the transfer characteristic. On the other hand, the transient current difference between devices No. 6 and No. 28 is almost unchanged at different junction temperatures. Therefore, a devices screening strategy based on the characteristic parameters measured at separate temperature conditions is better for actual parallel applications. That is, the on-resistance can be measured at the operating temperature and the transient parameters such as the threshold voltage and trans-conductance can be measured at room temperature.

Fig. 21. Current distribution at different temperatures.

V. JUNCTION TEMPERATURE VARIATION

Usually, thermal dissymmetry is a main cause of devices damage in parallel-connection applications. The junction temperature variation of paralleled devices due to current imbalance caused by device parameters spread should be further discussed. Generally, the device switches only twice for each test, and the increase of the device junction temperature due to the power loss is negligibly small. Thus, an actual converter needs to be built. However, the junction temperature is very difficult to measure. In this paper, a simple buck DC-DC converter model is built in LTSPICE as shown in Fig. 22. The device model is available from the manufacturer. A voltage source of 1V, an external capacitor of 180pF and a parasitic resistor of 15mΩ are added into the loop of one device to evaluate the influence of the main device parameters spread on the junction temperature variation.

Fig. 22. DC-DC buck converter model with two paralleled devices.

Generally, the case temperature is controlled within the range of 50℃-80℃, which depends on different cooling conditions [37]. In this paper, the initial case temperature of both devices is set as 80℃. The total steady-state current of the two paralleled devices is 40A. As shown in Fig. 23, the steady state current unbalance of the two paralleled devices is about 24%, and the transient current unbalance is about 28%. Moreover, the temperature variation of the two paralleled devices is about 4℃, and the corresponding difference of the temperature rising approaches 54%. If the circuit parameters and thermal path dissymmetry are also considered, this temperature variation gets larger. Therefore, more attention should be paid to the device parameter spread and screening in parallel-connection applications.

Fig. 23. Junction temperature variation of two paralleled devices.

VI. SCREENING GUIDELINE FOR PARALLELING

With the measurement results from the same production batch of SiC MOSFET devices, it can be seen that the spread of the threshold voltage is the largest, followed by those of the internal gate resistance, on-resistance and trans-conductance, in that order. Despite the fact that the spread of the gate-drain parasitic capacitance changes rapidly near the 12.5V region, the spreads of the other two parasitic capacitances almost remain constant with an increasing drain-source voltage. In addition, from comprehensive theoretical and experimental analyses of the effect of device parameters mismatches on the current distribution of paralleled SiC MOSFET devices, the most influential parameters are determined to be the on-resistance, threshold voltage, trans-conductance and gate-source parasitic capacitance.

For the steady-state current distribution, the device’s on-resistance has a significant effect and needs to be screened, while the other device parameters do not have a significant effect. The other device parameters have more influence on the transient current distribution than the steady-state current distribution. However, the effects of R_{G_int}, C_DS and C_GD on the transient current distribution are relatively small and can be ignored due to the small actual variations of their values. Therefore, the main factors affecting the transient current distribution are V_th, g_fs and C_GS. For the transient current distribution among paralleled SiC MOSFET devices, there is an overall effect, which may be an offsetting or a supporting function of the threshold voltage and trans-conductance. The overall effects of V_th and g_fs on the transient current distribution are complicated and depends on the relationship between their actual values. The influence of the difference of C_GS on the current distribution depends on the gate resistance. Whether the effects of △C_GS should be considered or not depends on the actual value of the selected gate resistance. In high frequency applications, the gate resistance is generally small and its effect can be ignored. In low switching speed applications, the effect of the difference of the gate-source capacitance can also be mitigated by adopting a partly decoupling driver configuration. Moreover, it is better to use main parameters measured at the operating temperature for device screening before parallel connection.

VII. CONCLUSIONS

This paper systematically discusses the spread of device parameters and their influence on the current distribution of paralleled SiC MOSFET devices. Test results shows that there is large parameter spread among SiC MOSFET devices from the same batch. Based on the control variable method, comprehensive theoretical and experimental analyses of the effect of device parameters mismatches on the current distribution among paralleled SiC MOSFET devices are conducted. Experimental results show that the main parameters that need to be screened are the threshold voltage, transconductance, on-resistance and gate-source capacitance. The temperature dependency of the spread of these main device parameters and their influence on current distribution are discussed. The transient current distribution is not sensitive to temperature. Meanwhile, the steady-state current distribution is affected by temperature. The device screening should consider the actual operating temperature of paralleled devices. In actual applications, if different main parameters need to be screened, which also depends on different driver configurations and switching speeds, a gate driver configuration is recommended to eliminate the influence of the spread of the gate-source capacitance. All of these suggestions are useful for the screening of devices or chips before device paralleling in power circuits or multi-chips paralleling in power modules.