• 전기전자학회논문지
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• 제24권2호
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• pp.619-625
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• 2020

본 논문에서는 Trench를 이용하여 기존 C-DMOSFET(Conventional DMOSFET)과 S-DMOSFET(Shielded DMOSFET) 구조보다 더 깊은 영역에 P+ shielding을 형성한 TS-DMOSFET(Trench Shielded DMOSFET) 구조를 제안하였으며 TCAD 시뮬레이션을 통해 C- 및 S-DMOSFET 구조와 전기적 특성을 비교하였다. 제안한 구조는 Source에 Trench를 형성한 후 도핑을 진행하므로 SiC 물질 특성과 관계없이 깊은 영역에 P+ shielding을 형성할 수 있다. 이로 인해 P-base에 인가되는 전압이 감소하여 리치스루 효과가 완화되었다. 그 결과 세 구조 모두 3.3kV의 항복 전압을 가질 때 제안한 구조의 온저항은 9.7mΩ㎠으로 C-DMOSFET과 S-DMOSFET의 온저항인 30.5mΩ㎠, 19.3mΩ㎠ 대비 각각 68%, 54% 개선된 온저항을 갖는다.

• 한국정밀공학회지
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• 제29권3호
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• pp.273-278
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• 2012

$ZrB_2$ has a melting temperature of $3245^{\circ}C$ and a low density of $6.1\;g/cm^3$, which makes this a candidate for application to ultra-high temperature over $2000^{\circ}C$. Beside these properties, $ZrB_2$ has excellent resistance to thermal shock and oxidation compared with other non-oxide engineering ceramics. This paper reviewed briefly 2 research examples, which are related to densification and properties of $ZrB_2$-based ceramics for ultra-high temperature applications. In the first section, the effect of $B_4C$ addition on the densification and properties of $ZrB_2$-based ceramics is shown. $ZrB_2$-20 vol.% SiC system was selected as a basic composition and $B_4C$ or C was added to this system in some extents. With sintered bodies, densification behavior and hightemperature (up to $1400^{\circ}C$) properties such as bending strength and hardness are examined. In the second section, the effect of the SiC size on the microstructures and physical properties is shown. $ZrB_2$-SiC ceramics are fabricated by using various SiC sources in order to investigate the grain-growth inhibition and the mechanical/thermal properties of $ZrB_2$-SiC.

• 한국재료학회지
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• 제8권7호
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• pp.621-627
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• 1998

단결정 Si(100) 기판과 비정질 Si 기판위에 Co/Zr 이중층을 이용하여 형성시킨 Co 실리사이드의 성장 거동에 대하여 연구하였다. 전자빔 증착기를 사용하여 단결정과 비정질 Si 기판위에 Zr $50\AA$과 Co $100\AA$을 차례로 증착한 박막을 50$0^{\circ}C$부터 $800^{\circ}C$까지 $100^{\circ}C$ 간격으로 질소 분위기에서 30초 동안 급속열처리를 하여 Co 실리사이드를 형성시켰다. 각 온도에서 열처리된 시편의 상형성, 화학적 조성, 계면의 형상, 전기적 특성을 XRD, AES, RBS, TEM, HRTEM 등으로 분석하였다. 분석 결과 $CoSi_2$ 상이 단결정 기판에서는 $700^{\circ}C$ 이상에서 기판과 정합성장을 하였고 비정질 기판에서는 다결정 성장을 하였으며 Co 실리사이드의 상형성 온도는 단결정 기판에서보다 비정질 기판에서 $100^{\circ}C$정도 낮아졌다. $CoSi_2$와 같은 Co rich 중간상은 두 기판 모두 형성되지 않았으며 초기 Co 실리사이드의 상형성 온도는 Co 단일층으로 상을 형성시킬 때 보다 더 높았다. Co 실리사이드와 Si 기판의 계면의 형상은 단결정 기판의 경우보다 비정질 기판에서 더 균질하였다. 박막의 면저항은 $600^{\circ}C$이하의 열처리 온도에서는 비정질 기판에서 형성된 Co 실리사이드 박막이 더 낮은 값을 나타내었고 그 이상의 열처리 온도에서는 단결정 기판에서 형성된 박막의 면저항값이 더 낮은 값을 나타내었으며 두가지 기판에서 형성된 박막 모두$ 800^{\circ}C$에서 가장 낮은 면저항 값을 보였다.TEX>$10^{-8}$ A/$\textrm{cm}^2$로 양질의 SrTiO$_3$박막을 제조하였다.는 과정에서 전세계 수준에서 멸종위기 식물을 목록화가 필요하다. 특히, 목록 작업이 완성되면 해당 분류군에 대한 기본적인 자료 수집과 장단기 조사과정으로서, 해당 분류군에 대한 멸종위협 요인을 수집하고, 이 자료를 근간으로 정량적으로 IUCN 적색목록 평가방식이 추진할 필요가 있다.he oscillations are active in the derived unit hydrograph. 3)The parameter estimates are validated by extending the model to the Soyang river Dam site with elimination of the autocorrelation in the disturbances. Finally, this paper illustrates the application of the multiple regression model to drive an optimal unit hydrograph dealing with the multicollinearity and the autocorrelation which cause some problems. 우선적으로 고려하여 사용할 농약을 선택해야 할 것으로 보이나, 그 외 약제의 잔류성, 사용량, 사용시기와 함께 기후조건, 토양의 투수성, 토층이 깊이, 지하수 깊이 등의 지역적인 특성들이 농약의 용탈잠재성에 미치는 영향도 더욱 구체적으로 파악되어야 할 것이며 농약의 선택 과정에서도 이러한 특성들이 앞으로 고려되어야 할 것이다.calenol 및 citrostadienol 등이 함유(含有)되어 있었다. 6. 4-desmethylsterol fraction에 는 sitosterol (74.6%)이

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권5호
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• pp.237-241
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• 2004

Amorphous silicon (a-Si) films are used in a broad range of solar cell, flat panel display, and sensor. Because of the greater ease of deposition and lower processing temperature, thin films are widely used for thin film transistors (TFTs). However, they have lower stability under the exposure of visible light and because of their low field effect mobility ($\mu$$_{FE}$ ) , less than 1 c $m^2$/Vs, they require a driving IC in the external circuits. On the other hand, polycrystalline silicon (poly-Si) thin films have superiority in $\mu$$_{FE}$ and optical stability in comparison to a-Si film. Many researches have been done to obtain high performance poly-Si because conventional methods such as excimer laser annealing, solid phase crystallization and metal induced crystallization have several difficulties to crystallize. In this paper, a new crystallization process using a molybdenum substrate has been proposed. As we use a flexible substrate, high temperature treatment and roll-to-roll process are possible. We have used a high temperature process above 75$0^{\circ}C$ to obtain poly-Si films on molybdenum substrates by a rapid thermal annealing (RTA) of the amorphous silicon (a-Si) layers. The properties of high temperature crystallized poly-Si studied, and poly-Si has been used for the fabrication of TFT. By this method, we are able to achieve high crystal volume fraction as well as high field effect mobility.

• 센서학회지
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• 제27권1호
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• pp.40-46
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• 2018

In this paper, we focus on optimization of a boron ($^{11}B$)-implanted n type Si epi substrate for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $125^{\circ}C$. The $^{11}B$-implantation on the N type-Si epi substrate formed isolation from the rest of the N-type Si by the depletion region of a PN junction. The TCR increased as the temperature of rapid thermal anneal (RTA) was increased at the temperature range from $900^{\circ}C$ to $1000^{\circ}C$ for the $p^+$ contact with implantation at dose of $1E16/cm^2$, but sheet resistance of this film was decreased. After the optimization of anneal process condition, the TCR of $1126.7{\pm}30.3$ (ppm/K) was obtained for the $p^-$ resistor-COB package chips contained $p^+$ contact with the implantation of $5E14/cm^2$. This shows the potential of the $^{11}B$-implanted n type Si epi substrate as a resistor for pressure sensor in thermal stable environment applications..

• 한국산업융합학회 논문집
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• 제26권6_1호
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• pp.967-976
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• 2023

Currently, with the thriving development in the field of solar energy, the widespread adoption of solar grid-connected power conversion systems is rapidly expanding. As the market continues to grow, the efficiency of solar power conversion systems is steadily increasing, while prices are rapidly decreasing. Photovoltaic panels often produce low output voltages, and Boost converters are commonly employed to elevate and stabilize these voltages. They are also utilized for implementing Maximum Power Point Tracking (MPPT), ensuring the full utilization of solar power generation. Recently, synchronous control techniques have been introduced, using controllable switching devices like Si IGBT or SiC MOSFET to replace the diodes in the original circuits. However, this has raised concerns related to costs. This paper offers a compromise solution, considering both the performance and economic factors of the converter. It proposes a hybrid high-efficiency synchronous converter structure that combines Si IGBT and SiC MOSFET. Additionally, the proposed topology has been practically implemented and tested, with results confirming its feasibility and cost-effectiveness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.354-357
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• 1999

This paper describes on the electrical and physical charateristics thin-film type Pt-RTD\\`s on Si wafers, in which MgO thin-films were used as medium layer in order to improve adhesion of Pt thin-films to SiO$_2$ layer. The MgO medium layer had the properties of improving Pt adhesion to SiO$_2$ and insulation without chemical reaction to Pt thin-films and the resistivity of Pt thin-films was improved. In the analysis of properties of Pt-RTD, TCR value had 3927 ppm/$^{\circ}C$ and liner in the temperature range of room temperature to 40$0^{\circ}C$

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.216-216
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• 2009

This paper describes a novel processing technique for the fabrication of polymer-derived SiCN (silicone carbonitride) microstructures for extreme microelectromechanical system (MEMS) applications. A polydimethylsiloxane (PDMS) mold was formed on an SU-8 pattern using a standard UV photolithographic process. Next, the liquid precursor, polysilazane, was injected into the PDMS mold to fabricate free-standing SiCN microstructures. Finally, the solid polymer SiCN microstructure was cross-linked using hot isostatic pressure at $400^{\circ}C$ and 205 bar. The optimal pyrolysis and annealing conditions to form a ceramic microstructure capable of withstanding temperatures over $1400^{\circ}C$ were determined. Using the optimal process conditions, the fabricated SiCN ceramic microstructure possessed excellent characteristics includingshear strength (15.2 N), insulation resistance ($2.163{\times}10^{14}\;{\Omega}$, and BDV (1.2 kV, minimum). Since the fabricated ceramic SiCN microstructure has improved electrical and physical characteristics compared to bulk Si wafers, it may be applied to harsh environments and high-power MEMS applications such as heat exchangers and combustion chambers.

• 한국정보통신학회논문지
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• 제5권6호
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• pp.1128-1135
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• 2001

본 논문에서는 HSG형성을 위한 Si$_2$H$_{6}$의 조사와 어닐링을 통한 seeding method를 64Mbit DRAM에 적용하였다. 이 기술을 사용함으로서 인이 도우핑된 Amorphous 실리콘의 전극에 HSG grain 크기를 조절할 수 있었고, 이 새로운 HSG형성조건은 기존의 stack 캐패시터보다 약 2배의 정전용량을 확보할 수 있었다. 이와같은 방법을 이용한 HSG형성에서 인농도, 저장폴리 증착온도 및 HSG의 두께에 대한 공정 최적 조건으로는 각각 3.0-4.OE19atoms/㎤ , 53$0^{\circ}C$ 및 400$\AA$이었다. 이들 최적화된 공정조건으로 64M bit DRAM 캐패시터에 적용시 질화막의 두께 한계는 65$\AA$으로 확인되었다.

• 한국전기전자재료학회논문지
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• 제20권8호
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• pp.661-665
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• 2007

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence $(<200^{\circ}C)$ on electrical properties. The feasible application in $1{\sim}2GHz$ frequency from measured data $BV_{CEO}{\sim}10V,\;f_T{\sim}14GHz,\;{\beta}{\simeq}110,\;NF{\sim}1dB$ using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.