• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.128-128
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• 2010

In this study, we investigated the evolution and reduction of the surface roughness during the high-speed chemical dry thinning process of Si wafers. The direct injection of NO gas into the reactor during the supply of F radicals from NF3 remote plasmas was very effective in increasing the Si thinning rate, due to the NO-induced enhancement of the surface reaction, but resulted in the significant roughening of the thinned Si surface. However, the direct addition of Ar and N2 gas, together with NO gas, decreased the root mean square (RMS) surface roughness of the thinned Si wafer significantly. The process regime for the increasing of the thinning rate and concomitant reduction of the surface roughness was extended at higher Ar gas flow rates. In this way, Si wafer thinning rate as high as $20\;{\mu}m/min$ and very smooth surface roughness was obtained and the mechanical damage of silicon wafer was effectively removed. We also measured die fracture strength of thinned Si wafer in order to understand the effect of chemical dry thinning on removal of mechanical damage generated during mechanical grinding. The die fracture strength of the thinned Si wafers was measured using 3-point bending test and compared. The results indicated that chemical dry thinning with reduced surface roughness and removal of mechanical damage increased the die fracture strength of the thinned Si wafer.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.99.2-99.2
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.392-392
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• 2010

In this study, high-speed chemical dry thinning process of Si wafer and evolution of surface roughness were investigated. Direct injection of NO gas into the reactor during the supply of F radicals from $NF_3$ remote plasmas was very effective in increasing the Si thinning rate due to the NO-induced enhancement of surface reaction but thinned Si surface became roughened significantly. Addition of Ar gas, together with NO gas, decreased root mean square (RMS) surface roughness of thinned Si wafer significantly. The process regime for the thinning rate enhancement with reduced surface roughness was extended at higher Ar gas flow rate. Si wafer thinning rate as high as $22.8\;{\mu}m/min$ and root-mean-squared (RMS) surface roughness as small as 0.75 nm could be obtained. It is expected that high-speed chemical dry thinning process has possibility of application to ultra-thin Si wafer thinning with no mechanical damage.

• Journal of Korea Foundry Society
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• v.33 no.2
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• pp.69-74
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• 2013

Silicon (Si) wafer was grown by using direct growth from Si melt and contaminations of wafer during the process were investigated. In our process, BN was coated inside of all graphite parts including crucible in system to prevent carbon contamination. In addition, coated BN layer enhance the wettability, which ensures the favorable shape of grown wafer by proper flow of Si melt in casting mold. As a result, polycrystalline silicon wafer with dimension of $156{\times}156$ mm and thickness of $300{\pm}20$ um was successively obtained. There were, however, severe contaminations such as BN and SiC on surface of the as-grown wafer. While BN powders were easily removed by brushing surface, SiC could not be eliminated. As a result of BN analysis, C source for SiC was from binder contained in BN slurry. Therefore, to eliminate those C sources, additional flushing process was carried out before Si was melted. By adding 3-times flushing processes, SiC was not detected on the surface of as-grown Si wafer. Polycrystalline Si wafer directly grown from Si melt in this study can be applied for the cost-effective Si solar cells.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.433-435
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• 1987

Thermal reoxidation was carried out to eliminate hole traps at the surface of Si wafer. As the result, the good surface state of wafer was obtained and hole traps were eliminate at the inversion layer. For the evaluation of reoxidation effects. MOS diode was fabricated and its C-Y curve was plotted.

• Tribology and Lubricants
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• v.35 no.3
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• pp.176-182
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• 2019

The primary objective of this study is to treat a monocrystalline silicon (Si) wafer having a thickness of $279{\mu}m$ by employing the ultrasonic nanocrystal surface modification (UNSM) technology for improving the efficiency and service life of nano-electromechanical systems (NEMSs) and micro-electromechanical systems (MEMSs) by enhancing of wear and corrosion resistances. The wear and corrosion resistances of the Si wafer were systematically investigated before and after UNSM treatment, wherein abrasive, oxidative and spalling wear mechanisms were applied to the as-received and subsequently UNSM-treated Si wafer. Compared to the asreceived state, the wear and corrosion resistances of the UNSM-treated Si wafer are found to be enhanced by about 23% and 14%, respectively. The enhancement in wear and corrosion resistances after UNSM treatment may be attributed to grain size refinement (confirmed by Raman spectroscopy) and modified surface integrity. Furthermore, it is observed that the Raman intensity reduced significantly after UNSM treatment, whereas neither the Raman shift nor new phases were found on the surface of the UNSM-treated Si wafer. In addition, the friction coefficient values of the as-received and UNSM-treated Si wafers are found to be about 0.54 and 0.39, respectively. Hence, UNSM technology can be effectively incorporated as an alternative mechanical surface treatment for NEMSs and MEMSs comprising Si wafers.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.26-32
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• 2012

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study will report the characteristic of wafer according to processing time, machining speed and pressure which have major influence on the abrasion of Si wafer polishing. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The characteristic of wafer surface according to processing condition is selected to use a result data that measure a pressure, machining speed, and the processing time. This result is appeared by the characteristic of wafer surface in machining condition. Through that, the study cans evaluation a wafer characteristic in variable machining condition. It is important to obtain optimal condition. Thus the optimum condition selection of ultra precision Si wafer polishing using load cell and infrared temperature sensor. To evaluate each machining factor, use a data through each sensor. That evaluation of abrasion according to variety condition is selected to use a result data that measure a pressure, machining speed, and the processing time. And optimum condition is selected by this result.

• Journal of the Korean Society for Precision Engineering
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• v.34 no.2
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• pp.107-114
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• 2017

In this investigation, we describe a metrological technique for surface and thickness profiles of a silicon (Si) wafer by using a 6 degree of freedom (DOF) stitching method. Low coherence scanning interferometry employing near infrared light, partially transparent to a Si wafer, is adopted to simultaneously measure the surface and thickness profiles of the wafer. For the large field of view, a stitching method of the sub-aperture measurement is added to the measurement system; also, 6 DOF parameters, including the lateral positioning errors and the rotational error, are considered. In the experiment, surface profiles of a double-sided polished wafer with a 100 mm diameter were measured with the sub-aperture of an 18 mm diameter at $10\times10$ locations and the surface profiles of both sides were stitched with the sub-aperture maps. As a result, the nominal thickness of the wafer was $483.2{\mu}m$ and the calculated PV values of both surfaces were $16.57{\mu}m$ and $17.12{\mu}m$, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.216-216
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• 2012

The purpose of this work is to investigate a back surface field (BSF) on variety wafer resistivity for industrial crystalline silicon solar cells. As pointed out in this manuscript, doping a crucible grown Cz Si ingot with Ga offers a sure way of eliminating the light induced degradation (LID) because the LID defect is composed of B and O complex. However, the low segregation coefficient of Ga in Si causes a much wider resistivity variation along the Ga doped Cz Si ingot. Because of the resistivity variation the Cz Si wafer from different locations has different performance as know. In the light of B doped wafer, we made wider resistivity in Si ingot; we investigated the how resistivities work on the solar cells performance as a BSF quality.