• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.214-217
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• 2006

p-type 비정질 실리콘 에미터와 n-type 실리콘 기판의 계면에 intrinsic 비정질 실리콘을 증착함으로써 계면의 재결합을 억제하여 20%가 넘는 효율을 보이는 이종접합 태양전지가 Sanyo에 의해 처음 제시된 후 intrinsic layer에 대한 연구가 많이 진행되어 왔다. 하지만 p-type wafer의 경우는 n-type에 비해 intrinsic buffer의 효과가 미미하거나 오히려 특성을 저하시킨다는 보고가 있으며 그 이유로는 minority carrier에 대한 barrier가 상대적으로 낮다는 것과 partial epitaxy가 발생하기 때문으로 알려져 있다. 본 연구에서는 partial epitaxy를 억제하기 위한 방법으로 증착 온도를 낮추고 QSSPC를 사용하여 minority carrier lifetime을 측정함으로써 각 온도에 따른 passivation 특성을 평가하였다. 또한 SiH4에 H2를 섞어서 증착하였을 경우 각 dilution ratio(H2 flow/SiH4 flow)에서의 passivation 특성 또한 평가하였다. 기판 온도 $100^{\circ}C$에서 증착된 샘플의 lifetime이 가장 길었으며 그 이하와 이상에서는 lifetime이 감소하는 경향을 보였다 낮은 온도에서는 박막 자체의 결함이 증가하였기 때문이며 높은 온도에서는 partial epitaxy의 영향으로 추정된다. H2 dilution을 하여 증착한 샘플의 경우 SiH4만 가지고 증착한 샘플보다 훨씬 높은 lifetime을 가졌다 이 또한 박막 FT-IR결과로부터 H2 dilution을 한 경우 compact한 박막이 형성되는 것을 확인할 수 있었는데 radical mobility 증가에 의한 박막 특성 향상이 원인으로 생각된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.471-475
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• 2000

P-type (100) Si wafer patterned with 1000$\AA$ SiO$_2$island was used as substrate and the Si films were deposited under low pressure using Si$_2$H$_{6}$-H$_2$gas mixture where the total gas flow rate and deposition pressure were 16.6sccm and 3.5mtorr, respectively. In this condition, we selectively obtained high-quality epitaxial Si layer of the 350~1050$\AA$ thickness. In order to extend the incubation period, we kept high pressure H$_2$ environment without Si$_2$H$_{6}$ gas for few minutes after first incubation period and then we conformed the existence of second incubation period.iod.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.10
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• pp.779-783
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• 2011

The morphology of etch pits in commercial 4H-SiC epi-wafer were investigated by molten-KOH etching. The etching process was optimized in $525{\sim}570^{\circ}C$ at 2~10 min and the novel type of etch pits was revealed. This type of etch pits have been considered as TED (threading edge dislocation) II, its origin and nature, however, are not reported yet. In this work, the morphology and evolution of etch pits during epitaxial growth were analyzed and the different behavior between TED and TEDII was discussed.

• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.73-81
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• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.34 no.4
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• pp.139-142
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• 2024

Along with the use of wide bandgap energy materials such as SiC and GaN in power semiconductors and the development trend of devices, many research results have been reported, including the success of research on AlN single crystals with higher energy gaps and the development of 2-inch single crystal wafers. However, AlN single crystals grown using chemical vapor deposition have been developed into thin films less than a few micrometers thick, but there are almost no results with thicknesses greater than that. Therefore, in this study, we attempted to grow by applying HVPE (Hydride vapor phase epitaxy), one of the chemical vapor deposition methods. The grown AlN single crystal was manufactured using self-designed equipment, and we attempted to establish the conditions for manufacturing AlN single crystals on sapphire wafer. We would like to characterize the growth behavior through an optical microscope observation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.6
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• pp.256-259
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• 2006

The amorphous $SiO_x$ nanowires were synthesized by the vapor phase epitaxy (VPE) method. $SiO_x$ nanowires were formed on silicon wafer of temperatures ranged from $800{\sim}1100^{\circ}C$ and nickel thin film was used as a catalyst for the growth of nanowires. A vapor-liquid-solid (VLS) mechanism is responsible for the catalyst-assisted amorphous $SiO_x$ nanowires synthesis in this experiment. The SEM images showed cotton-like nanostructure of free standing $SiO_x$ nanowires with the length of more than about $10{\mu}m$. The $SiO_x$ nanowires were confirmed amorphous structure by TEM analysis and EDX spectrum reveals that the nanowires consist of Si and O.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.76-84
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• 1994

The characteristics of 3 inch wafer scale GaAs epitaxial wafer grown by molecular beam epitaxy for LSI process application were studied. The thickness and doping uniformity are characterized and discussed. The growth temperature and growth rate were $600^{\circ}C$ by pyrometer, and 1 $\mu$m/h, respectively. It was found that thickness and doping uniformity were 3.97% and 4.74% respectively across the full 3 inch diameter GaAs epitaxial layer. Also, ungated MESFETs have been fabricated and saturation current measurement showed 4.5% uniformity on 3 inch, epitaxial layer, but uniformity of threshold voltage increase up to 9.2% after recess process for MESFET device.

• Journal of the Korean Vacuum Society
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• v.11 no.1
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• pp.16-21
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• 2002

Selective epitaxial growth(SEG) of silicon were performed at low temperature under an ultraclean environment below $1000^{\circ}C$ using ultraclean $Si_2H_6$ and $H_2$ gases ambient in low pressure chemical vapor deposition(LPCVD). As a result of ultraclean processing, epitaxial Si layers with good quality were obtained for uniform and SEG wafer at temperatures range 600~$710^{\circ}C$ and an incubation period of Si deposition only on $SiO_2$ was found. Low-temperature Si selectivity deposition condition and epitaxy on Si were achieved without addition of HCl. The epitaxial layer was found to be thicker than the poly layer deposited over the oxide. Incubation period prolonged for 20~30 sec can be obtained by $O_2$addition. The surface morphologies & cross sections of the deposited films were observed with SEM, The structure of the Si films was evaluated XRD.

• Current Photovoltaic Research
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• v.6 no.4
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• pp.109-118
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• 2018

Silicon (Si) solar cells are the most successful technology which are ruling the present photovoltaic (PV) market. In that essence, multijunction (MJ) solar cells provided a new path to improve the state-of-art efficiencies. There are so many hurdles to grow the MJ III-V materials on Si substrate as Si with other materials often demands similar qualities, so it is needed to realize the prospective of Si tandem solar cells. However, Si tandem solar cells with MJ III-V materials have shown the maximum efficiency of 30 %. This work reviews the development of the III-V/Si solar cells with the synopsis of various growth mechanisms i.e hetero-epitaxy, wafer bonding and mechanical stacking of III-V materials on Si substrate. Theoretical approaches to design efficient tandem cell with an analysis of state-of-art silicon solar cells, sensitivity, difficulties and their probable solutions are discussed in this work. An analytical model which yields the practical efficiency values to design the high efficiency III-V/Si solar cells is described briefly.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.657-662
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• 2003

This paper presents a new fabrication method of selective SiGe epitaxial growth at 650 $^{\circ}C$ on (100) silicon wafer with oxide patterns by reduced pressure chemical vapor deposition. The new method is characterized by a cyclic process, which is composed of two parts: initially, selective SiGe epitaxy layer is grown on exposed bare silicon during a short incubation time by SiH$_4$/GeH$_4$/HCl/H$_2$system and followed etching step is achieved to remove the SiGe nuclei on oxide by HCl/H$_2$system without source gas flow. As a result, we noted that the addition of HCl serves not only to reduce the growth rate on bare Si, but also to suppress the nucleation on SiO$_2$. In addition, we confirmed that the incubation period is regenerated after etching step, so it is possible to grow thick SiGe epitaxial layer sustaining the selectivity. The effect of the addition of HCl and dopants incorporation was investigated.