• 한국정보통신학회논문지
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• 제10권12호
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• pp.2258-2263
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• 2006

본 논문은 shallow trench isolation (STI) 공정에서 ILD (inter-layer dielectric) 막의 수분에 의해 야기되는 단 채널 (short-channel) nMOSFET의 hump 특성의 원인을 분석하고 억제 방법을 제안하였다. 다양한 게이트를 가지는 소자와 TDS-APIMS(Thermal Desorption System-Atmospheric Pressure Ionization Mass Spectrometry) 측정을 이용하여 hump 특성을 체계적으로 분석하였고, 분석을 바탕으로 단 채널 hump모델을 제안하였다. 제안된 모델에 의한 단 채널 nMOSFET의 hump 현상은 poly-Si 게이트 위의 ILD 막의 수분이 상부의 SiN 막에 의해 밖으로 확산되지 못하고 게이트와 STI의 경계면으로 확산하여 발생한 것이 며, 이를 개선하기 위해 상부의 SiN 막의 증착 전 열공정을 통해 ILD 막의 수분을 효과적으로 배출시킴으로써 hump 특성을 성공적으로 억제하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.789-792
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• 2003

pMOSFET having 10 ${\mu}um$ thickness Gd layer has been tested to be used as a slow neutron sensor. The total thermal neutron cross section for the Gd is 47,000 barns and the cross section value drops rapidly with increasing neutron energy. When slow neutrons are incident to the Gd layer, the conversion electrons are emitted by the neutron absorption process. The conversion electrons generate electron-hole pairs in the $SiO_2$ layer of the pMOSFET. The holes are easily trapped in Oxide and act as positive charge centers in the $SiO_2$ layer. Due to the induced positive charges, the threshold turn-on voltage of the pMOSFET is changed. We have found that the voltage change is proportional to the accumulated slow neutron dose, therefore the pMOSFET having a Gd nuclear reaction layer can be used for a slow neutron dosimeter. The Gd-pMOSFET were tested at HANARO neutron beam port and $^{60}CO$ irradiation facility to investigate slow neutron response and gamma response respectively. Also the pMOSFET without Gd layer were tested at same conditions to compare the characteristics to the Gd-pMOSFET. From the result, we have concluded that the Gd-pMOSFET is very sensitive to the slow neutron and can be used as a slow neutron dosimeter. It can also be used in a mixed radiation field by subtracting the voltage change value of a pMOSFET without Gd from the value of the Gd-pMOSFET.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.190-191
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• 2013

본 논문에서는 기존의 Si MOSFET을 사용한 전력시스템과 비교하여 WBG(Wide Band Gap)특성을 갖는 GaN(Gallium Nitride) FET을 사용한 전력시스템을 비교 분석한다. 대표성을 갖는 평가가 가능하도록 가장 일반적인 FB 구조를 대상으로 Si MOSFET과 GaN FET을 각각 적용하고, 다양한 기준 조건에서 효율과 전력 밀도 등 성능을 비교한다. 전체 과정은 수학적 계산 및 시뮬레이션으로 검증한다.

• Journal of Power Electronics
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• 제18권4호
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• pp.985-996
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• 2018

The implementation and performance evaluation of an interleaved boundary conduction mode (BCM) boost power factor correction (PFC) converter is presented in this paper by employing three wide band-gap switching devices: a super junction silicon (Si) MOSFET, a silicon carbide (SiC) MOSFET and a gallium nitride (GaN) high electron mobility transistor (HEMT). The practical considerations for adopting wide band-gap switching devices to BCM boost PFC converters are also addressed. These considerations include the gate drive circuit design and the PCB layout technique for the reliable and efficient operation of a GaN HEMT. In this paper it will be shown that the GaN HEMT exhibits the superior switching characteristics and pronounces its merits at high-frequency operations. The efficiency improvement with the GaN HEMT and its application potentials for high power density/low profile BCM boost PFC converters are demonstrated.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.275-276
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• 2019

본 논문에서는 SiC MOSFET을 적용한 10kW급 배터리 충전장치용 3상 PWM 정류기를 개발한다. 개발한 정류기는 3상 Bridge에 IGBT를 대체할 수 있는 WBG 전력반도체 SiC MOSFET을 적용하여 스위칭 주파수 향상 및 고전력밀도를 달성하였다. 개발한 10kW급 3상 PWM 정류기의 효율 및 THD 성능을 실험을 통해 검증한다.

• Journal of Power Electronics
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• 제19권2호
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• pp.591-601
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• 2019

With the development of renewable energy, grid-connected inverter technology has become an important research area. When compared with traditional silicon IGBT power devices, the silicon carbide (SiC) MOSFET shows obvious advantages in terms of its high-power density, low power loss and high-efficiency power supply system. It is suggested that this technology is highly suitable for three-phase AC motors, renewable energy vehicles, aerospace and military power supplies, etc. This paper focuses on the SiC MOSFET behaviors that concern the parasitic component influence throughout the whole working process, which is based on a three-phase grid-connected inverter. A high-speed model of power switch devices is built and theoretically analyzed. Then the power loss is determined through experimental validation.

• ETRI Journal
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• 제25권3호
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• pp.203-209
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• 2003

This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.

• ETRI Journal
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• 제28권2호
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• pp.253-256
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• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.21-22
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• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.

• 전기전자학회논문지
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• 제28권1호
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• pp.46-52
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• 2024

이번 연구에서 우리는 게이트 산화막을 형성하기 위해 Si을 증착한 후 산화시킨 SiC MOSFET의 전기적 특성을 연구했다. 고품질의 Si/SiO₂ 계면을 제작하기 위해 얇은 Si 층을 SiC epi 층 위에 약 20 nm을 증착한 후 산화하여 게이트 산화막을 약 55 nm로 형성했다. SiC를 산화하여 게이트 산화막을 제작한 소자와 계면 트랩 밀도, 온저항, 전계-효과 이동도의 측면에서 비교했다. 위 소자는 향상된 계면 트랩 밀도 (~8.18 × 10¹¹ eV^-1cm^-2), 전계-효과 이동도 (27.7 cm²/V·s), 온저항 (12.9 mΩ·cm²)을 달성하였다.