• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.31-33
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• 2020

본 논문은 고효율 11kW급 양방향 탑재형 충전기에 대한 연구결과를 발표한다. 토폴로지로는 3상 2-레벨 인버터와 CLLLC 공진형 컨버터를 적용하였으며, 모든 전력반도체 소자는 SiC-MOSFET를 적용하였다. CLLLC 공진형 컨버터의 고효율 달성을 위해, 배터리 전압에 따라 DC 링크 전압 가변 알고리즘을 적용하였으며 양방향 동작시 정류단이 동기 정류기로 동작하도록 설계하였다. 인버터 스위칭 주파수 20kHz, CLLLC 공진형 컨버터 스위칭 주파수 80~300kHz, 배터리 전압 213~413V, 계통 전압 380V/60Hz 사양으로 프로토타입을 설계/제작하였으며 순방향 전력전달 최대 효율 95.8%이상, 역방향 전력전달시 최대효율 95.1%이상의 결과를 달성하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.2
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• pp.133-140
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• 2024

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.5
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• pp.536-541
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• 2003

In order to avoid oxygen contamination on the diamond surface as far as possible during the device process, the A1/Ca $F_2$/diamond MISFET(metal-insulator-semiconductor field-effect transistor) was prepared by ultrahigh vacuum process and its electrical properties were investigated. The surface conductive layer of fluorinated diamond surface was employed for the conducting channel of the MISFET. The observed effective mobility(${\mu}$e$\_$ff/) of the MISFET was 300 c $m^2$/Vs, which is the highest value obtained until now in the diamond FET. Besides, the measured surface state density of the device was ∼10$\^$11//c $m^2$ eV, which is comparable with conventional Si MOSFET$\_$s/(metal-oxide-semiconductor field-effect-transistors). This work is the first report of the fluorinated diamond MISFET prepared by ultrahigh vacuum process and its application to inverter circuit.

• ETRI Journal
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• v.14 no.1
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• pp.40-51
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• 1992

$0.25{\mu} m$ 급 pMOSFET소자를 구현하기 위해, $P^+$ 폴리실리콘을 적용한 pMOS를 제작하였으며, $p^+$ 폴리실리콘 게이트 소자에서 심각하게 문제가 되고 있는 붕소이온 침투현상을 조사하고 붕소이온 침투가 일어나지 않는 최적열처리온도를 조사하였다. 소자제조 공정중 게이트 공정만 전자선 (EBML300)을 이용하여 직접묘사하고 그 이외의 공정은 stepper(gline) 을 사용하는 Mix & Match 방법을 사용하였다. 또한 붕소이온 침투현상을 억제하기 위한 한가지 예로서, 실리콘산화막과 실리콘질화막을 적층한 ONO(Oxide/Nitride/Oxide) 구조를 게이트 유전체로 적용한 소자를 제작하여 그 가능성을 조사하였다. 그 결과 $850^{\circ}C$의 온도와 $N_2$ 분위기에서 30분동안 열처리 하였을 경우, 붕소이온의 침투현상이 일어나지 않음을 SIMS(Secondary Ion Mass Spectrometer) 분석 및 C-V(Capacitance-Voltage) 측정으로 확인할 수 있었으며 그 이상의 온도에서는 붕소이온이 침투되어 flat band전압(Vfb)을 변화시킴을 알았다. 6nm의 얇은 게이트 산화막 및 $0.1{\mu} m$ 이하의 LDD(Lightly Doped Drain) $p^-$의 얇은 접합을 형성함으로써 소자의 채널길이가 $0.2 {\mu} m$까지 짧은 채널효과가 거의 없는 소자제작이 가능하였으며, 전류구동능력은 $0.26\muA$/$\mu$m(L=0.2$\mu$m, V$_DS$=2.5V)이었고, subthreshold 기울기는 89-85mV/dec.를 얻었다. 붕소이온의 침투현상을 억제하기 위한 한가지 방법으로 ONO 유전체를 소자에 적용한 결과, $900^{\circ}C$에서 30분의 열처리조건에서도 붕소이온 침투현상이 일어나지 않음으로 미루어 , $SiO_2$ 게이트 유전체보다 ONO 게이트 유전체가 boron 침투에 대해서 좋은 장벽 역활을 함을 알았다. ONO 게이트 유전체를 적용한 소자의 경우, subthreshold특성은 84mV/dec로서 좋은 turn on,off 특성을 얻었으나, ONO 게이트 유전체는 막자체의 누설전류와 실리콘과 유전체 계면의 고정전하량인 Qss의 양이 공정조건에 따라 변화가 심해서 문턱전압 조절이 어려워 소자적용시 문제가 된다. 최근 바닥 산화막(bottom oxide) 두께가 최적화된 ONO 게이트 유전체에 대하 연구가 활발히 진행됨을 미루어, 바닥 산화막 최적화가 된다면 더 좋은 결과가 예상된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.27-34
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• 2004

The study on the RF substrate circuit is necessary to model RF output characteristics of deep submicron MOSFETs below 0.2$\mum$ gate length that have bun commercialized by the recent development of Si submicron process. In this paper, direct extraction methods are developed to apply for a simple substrate resistance model as well as another substrate model with connecting resistance and capacitance in parallel. Using these extraction methods, better agreement with measured Y22-parameter up to 30 GHz is achieved for 0.15$\mum$ CMOS device by using the parallel RC substrate model rather than the simple resistance one, demonstrating the RF accuracy of the parallel model and extraction technique. Using this model, bias and gate length dependent curves of substrate parameters in the RF region are obtained by increasing drain voltage of 0 to 1.2V at deep submicron devices with various gate lengths of 0.11 to 0.5㎛ These new extraction data will greatly contribute to developing a scalable RF nonlinear substrate model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.291-292
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• 2012

MOSFET 구조에서 metal oxide에 기반을 둔 게이트 유전체의 연구는 실리콘(Si)을 기반으로 한 반도체 발명이래로 가장 인상적인 발전을 이뤄 왔다. 이는 metal oxide의 높은 유전상수 특성이 $SiO_2$보다 우수하고, 유전체 박막의 두께 감소로 인한 전기적 특성 저하를 보완하기 때문이다. 특히 지난 10년 동안, Hafnium에 기반을 둔 $HfO_2$는 차세대 반도체용 유전 물질로 전기적 구조적 특성에 대한 연구가 활발히 진행되어왔다. 그러나 현재까지 $HfO_2$에 대한 nano-mechanical 특성 연구는 미미하여 이에 대한 연구가 필요하다. 이에 본 연구에서는 Hf 및 $HfO_2$ 박막의 증착 및 열처리 조건을 다르게 하여 실험을 진행하였다. 시료는 rf magnetron sputter를 이용하여 Si 기판위에 Hafnium target으로 산소유량(4, 6 sccm)을 달리하여 증착하였고, 이후 furnace에서 400에서 $800^{\circ}C$까지 질소분위기에서 20분간 열처리를 실시하였다. 실험결과 산소 유량을 6 sccm으로 증착한 시료의 current density 성능이 모든 열처리 과정에서 증가하였다. Nano-indenter로 측정하고 Weibull distribution으로 정량적 계산을 한 경도 (Hardness)는 as-deposited 시료를 기준으로 $400^{\circ}C$에서는 감소했으나 온도가 높아질수록 증가하였다. 특히, $400^{\circ}C$ 열처리한 시료에서 산소농도에(4 sccm : 5.35 GPa, 6 sccm : 6.15 GPa)따른 두 시료간의 변화가 가장 두드러졌다. 반면에, 탄성계수 (Elastic modulus)는 산소농도 6 sccm을 넣고 증착된 시료들이 4 sccm을 넣고 증착한 시료보다 모두 높은 값을 나타냈다. 또한, $800^{\circ}C$ 열처리한 시료에서 산소농도에(4 sccm : 128.88 GPa, 6 sccm : 149.39 GPa)따라 표면의 탄성에 큰 차이가 있음을 확인하였다. 이는 증착된 $HfO_2$ 시료들이 비정질 상태에서 $HfO_2$로 결정화되는 과정에서 산소가 증가할수록 박막의 defect이 감소되기 때문으로 사료된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.427-435
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• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.