• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.65-65
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• 1999

Dry etching technique provides more easy controllability on the etch profile such as anisotropic etching than wet etching process and the results of lots of researches on the characterization of various plasmas or ion beams for semiconductor etching have been reported. Chlorine-based plasmas or chlorine ion beam have been often used to etch several semiconductor materials, in particular Si-based materials. We have studied the effect of He flow rate on the Si and SiO2 dry etching using chlorine-based plasma. Experiments were performed using reactive ion etching system. RF power was 300W. Cl2 gas flow rate was fixed at 58.6 sccm, and the He flow rate was varied from 0 to 120 sccm. Fig. 1 presents the etch depth of si layer versus the etching time at various He flow rate. In case of low He flow rate, the etch rate was measured to be negligible for both Si and SiO2. As the He flow increases over 30% of the total inlet gas flow, the plasma state becomes stable and the etch rate starts to increase. In high Ge flow rate (over 60%), the relation between the etch depth and the time was observed to be nearly linear. Fig. 2 presents the variation of the etch rate depending on the He flow rate. The etch rate increases linearly with He flow rate. The results of this preliminary study show that Cl2/He mixture plasma is good candidate for the controllable si dry etching.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.331-332
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• 2007

Surface micromachined SiC devices have readily been fabricated from the polycrystalline (poly) 3C-SiC thin film which has an advantage of being deposited onto $SiO_2$ or $Si_3N_4$ as a sacrificial layer. Therefore, in this work, magnetron reactive ion etching process which can stably etch poly 3C-SiC thin films grown on $SiO_2$/Si substrate at a lower energy (70 W) with $CHF_3$ based gas mixtures has been studied. We have investigated the etching properties of the poly 3C-SiC thin film using PR/Al mask, according to $O_2$ flow rate, pressure, RF power, and electrode gap. The etched RMS (root mean square), etch rate, and etch profile of the poly 3C-SiC thin films were analyzed by SEM, AFM, and $\alpha$-step.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.51-56
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• 2012

In order to fabricate through-Si-vias for thermal vias by using wet etching process, anisotropic etching behavior of Si substrate was investigated as functions of concentration and temperature of TMAH solution in this study. The etching rate of 5 wt%, 10 wt%, and 25 wt% TMAH solutions, of which temperature was maintained at $80^{\circ}C$, was $0.76{\mu}m/min$, $0.75{\mu}m/min$, and $0.30{\mu}m/min$, respectively. With changing the temperature of 10 wt% TMAH solution to $20^{\circ}C$ and $50^{\circ}C$, the etching rate was reduced to $0.067{\mu}m/min$ and $0.233{\mu}m/min$, respectively. Through-Si-vias of $500{\mu}m$-depth could be fabricated by etching a Si substrate for 5 hours in 10 wt% TMAH solution at $80^{\circ}C$ after forming same via-pattern on each side of the Si substrate.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.19-23
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• 2012

Silicon substrate for light emitting diodes (LEDs) has been the tendency of LED packaging for improving power consumption and light output. In this study, a low cost and high throughput Si through via fabrication has been demonstrated using a wet etching process. Both a wet etching only process and a combination of wet etching and dry etching process were evaluated. The silicon substrate with Si through via fabricated by KOH wet etching showed a good electrical resistance (${\sim}5.5{\Omega}$) of Cu interconnection and a suitable thermal resistance (4 K/W) compared to AlN ceramic substrate.

• Journal of information and communication convergence engineering
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• v.5 no.3
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• pp.215-218
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• 2007

In this paper, amorphous semiconductor and insulator thin film are etched using reactive ion etcher. At that time, we experiment in various RIE conditions (chamber pressure, gas flow rate, rf power, temperature) that have effects on quality of thin film. The using gases are $CF_4,\;CF_4+O_2,\;CCl_2F_2,\;CHF_3$ gases. The etching of a-Si:H thin film use $CF_4,\;CF_4+O_2$ gases and the etching of $a-SiO_2,\;a-SiN_x$ thin film use $CCl_2F_2,\;CHF_3$ gases. The $CCl_2F_2$ gas is particularly excellent because the selectivity of between a-Si:H thin film and $a-SiN_x$ thin film is 6:1. We made precise condition on dry etching with uniformity of 5%. If this dry etching condition is used, that process can acquire high yield and can cut down process cost.

• Electrical & Electronic Materials
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• v.9 no.3
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• pp.291-297
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• 1996

The surface properties of AI(Si, Cu) alloy film after plasma etching using the chemistries of chlorinated and fluorinated gases with varying the etching time have been investigated using X-ray Photoelectron Spectroscopy. Impurities of C, Cl, F and O etc are observed on the etched AI(Si, Cu) films. After 95% etching, aluminum and silicon show metallic states and oxidized (partially chlorinated) states, copper shows Cu metallic states and Cu-Cl$_{x}$(x$_{x}$ (x$_{x}$ (1

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.4
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• pp.749-753
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• 2010

We investigated the haze and the surface roughness of textured Si substrates etched by $XeF_2$ etching system with the etching parameters of $XeF_2$ pressure, etching time, and etching cycle. Here the haze was obtained as a function of wavelength from the measured reflectance. The haze of textured Si substrates was strongly affected by the etching parameter of etching cycle. The surface roughness of textured Si substrates was calculated with the haze and the scalar scattering theory at the wavelength of 800 nm. Then, the surface roughness was compared with that measured by atomic force microscope. The surce roughness obtained by two methods was changed with the similar tendency n terms of $XeF_2$ etching conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.616-621
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• 2009

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.892-895
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• 2003

This paper describes on RIE(Reactive Ion Etching) characteristics of 3C-SiC(Silicon Carbide) grown on Si(100) wafers. During RIE of 3C-SiC films in this work, $CHF_3$ gas is used to form of polymer as a side wall for excellent anisotropy etching. From this process, etch rates are obtained a $60{\sim}980{\AA}/min$ by various conditions such as $CHF_3$ gas flux, $O_2$ addition ratio, RF power and electrode distance. Also, approximately $40^{\circ}$ mesa structures are successfully formed at 100 mTorr $CHF_3$ gas flow ratio, 200 W RF power and 30 mm electrode distance. Moreover, vertical side wall is fabricated by anisotropy etching with 50% $O_2$ addition ratio and 25 mm electrode distance. Therefore, RIE of 3C-SiC films using $CHF_3$ could be applicable as fabrication process technology for high-temperature 3C-SiC MEMS applications.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.27.2-27.2
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• 2010

In recent years, there is a strong requirement of low cost, stable microelectro mechanical systems (MEMS) for resonators, microswitches and sensors. Most of these devices consist of freely suspended microcantilevers, which are usually made by the etching of some sacrificial materials. Herein, we have attempted to use Si nanowires, inherited from the parent Si wafer, as a sacrificial material due to its porosity, low cost and ease of fabrication. Prior to the fabrication of the Si nanowires silver nanoparticles were continuously formed on the surface of Si wafer. Vertically aligned Si nanowires were fabricated from the parent Si wafers by aqueous chemical route at $50^{\circ}C$. Afterwards, the morphological and structural characteristics of the Si nanowires were investigated. The morphology of nanowires was strongly modulated by the resistivity of the parent wafer. The 3-step etching of nanowires in diluted KOH solution was carried out at room temperature in order to control the fast etching. A layer of $Si_3N_4$ (300 nm) was used for the selective fabrication of nanowires. Finally, a freely suspended bridge of zinc oxide (ZnO) was fabricated after the removal of nanowires from the parent wafer. At present, we believe that this technique may provide a platform for the inexpensive fabrication of futuristic MEMS.