• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.1
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• pp.21-25
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• 2009

By using Si CMOS process, small RFID tag antenna were fabricated on Si substrate and their electrical properties were evaluated. Firstly, tag antenna pattern and the electromagnetic properties were simulated with HFSS. The frequency was 13.56 MHz, the line-width and line-gap were modeled in the range of $50{\sim}200{\mu}m$. S parameters, SRF, and Q value were calculated from geometry. When the line-width and line-gap were $100{\mu}m$ and $100 {\mu}m$, respectively and the loop-turn was 10, the SRF was 80 MHZ and the Q value was ca. 9. When the microstrip antenna pattern of aluminum $2{\mu}m$ was fabricated by using DC sputtering, Vpp of ca. 4.3 V was obtained when the reader and tag were closely contacted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.1-9
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• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.500-505
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• 1997

Experimental amorphous photodiode is fabricated on CMOS IC using a-Si:H p-i-n structure. Amorphous photodiode is scuccessfully integrated on CMOS IC using amorphous Si produced by PECVD system. The PECVD system can deposit a-Si:H at low temperature so that photodiode can be integrated with CMOS IC structure without any process incompatibility. The fabricated amorphous photodiode has a breakdown voltage of below -20 V, a leakage current of about 1 $\mu\textrm{A}$, and turn-on voltage of 0.6~0.8 V. It is demonstrated that the photocurrent of optical signal can be turned on and off by a small voltage and the fabricated amorphous p-i-n photodiode can be used as an optical switch.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.167-170
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• 2002

The influence of Si surface damage on Ni-silicide with TiN Capping layer and the effect of $H_2$ anneal are characterized. Si surface is intentionally damaged using Ar Sputtering. The sheet resistance of NiSi formed on damaged silicon increased rapidly as Ar sputtering time increased. However, the thermal stability of Ni-Si on the damage silicon was more stable than that on at undamaged Si, which means that damaged region retards the formation of NiSi. It was shown that $H_2$ anneal and TiN capping is highly effective in reducing NiSi sheet resistance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• Journal of the Optical Society of Korea
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• v.12 no.4
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• pp.217-220
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• 2008

An optical receiver using a CMOS-compatible avalanche photodetector (CMOS-APD) is demonstrated. The CMOS-APD is fabricated with $0.18{\mu}m$ standard CMOS technology and the optical receiver is implemented by using the CMOS-APD and a transimpedance amplifier on a board. The optical receiver can detect 6.25-Gb/s data with the help of the series inductive peaking effect.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.