• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2004년도 춘계학술대회
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• pp.62-64
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• 2004

초고속 RF IC의 핵심소자인 SiGe에피텍시층을 가진 이종양극트란지스터 (hetero junction bipolar transistor: HBT)를 0.35um급 CMOS공정으로 제작하였다. 이때 IOW $V_{BE}$영역에서의 Current Gain의 선형성을 향상시키기 위하여 Capping 실리콘의 두께를 200과 300${\AA}$으로 나누고 EDR (Emitter Drive-in RTA)의 온도와 시간을 900$\~$1000C, 0$\~$30sec로 각각 변화시키면서 최적조건을 알아보았다. 실험범위 내에서의 최적공정조건은 300${\AA}$의 capping 실리콘과 975C-30sec의 EDR조건이었다.

• 한국재료학회지
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• 제17권2호
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국재료학회지
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• 제16권9호
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• pp.571-577
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• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• Journal of the Optical Society of Korea
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• 제17권5호
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• pp.433-440
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• 2013

We present an experimental and numerical study of spectral profiles of effective group indices of hydrogenated amorphous silicon (a-Si:H) waveguides and of their chromatic-dispersion effect on the four-wave-mixing (FWM) signal generation. The a-Si:H waveguides of 220-nm thickness and three different widths of 400, 450 and 500 nm were fabricated by using the conventional CMOS device processes on a $2-{\mu}m$ thick $SiO_2$ bottom layer deposited on 8-inch Si wafers. Mach-Zehnder interferometers (MZIs) were formed with the a-Si:H waveguides, and used for precise measurement of the effective group indices and thus for determination of the spectral profile of the waveguides' chromatic dispersion. The wavelength ranges for the FWM-signal generation were about 45, 75 and 55 nm for the 400-, 450- and 500-nm-wide waveguides, respectively, at the pump wavelength of 1532 nm. A widest wavelength range for the efficient FWM process was observed with the 450-nm-wide waveguide having a zero-dispersion near the pump wavelength.

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.47-54
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• 2006

본 논문에서는 초광대역 통신시스템 응용을 위한 이중채널 6b 1GS/s A/D 변환기 (ADC)를 제안한다. 제안하는 ADC는 IGS/s의 신호처리속도에서 전력, 칩 면적 및 정확도를 최적화하기 위해 인터폴레이션 기반의 6b 플래시 ADC 회로로 구성되며, 입력 단에 광대역 열린 루프 구조의 트랙-앤-홀드 증폭기를 사용하였으며, 넓은 입력신호범위를 처리하기 위한 이중입력의 차동증폭기와 함께 래치 단에서의 통상적인 킥-백 잡음 최소화기법 등을 적용한 비교기를 제안하였다. 또한, CMOS 기준 전류 및 전압 발생기를 온-칩으로 집적하였으며, 디지털 출력에서는 새로운 버블 오차 교정회로를 제안하였다. 본 논문에서 제안하는 ADC는 0.18um 1P6M CMOS 공정으로 제작되었으며, 1GS/s의 동작속도에서 SNDR 및 SFDR은 각각 최대 30dB, 39dB를 보이며, 측정된 시제품 ADC의 DNL 및 INL은 각각 1.0LSB, 1.3LSB 수준을 보여준다. 제안하는 이중채널 ADC의 칩 면적은 $4.0mm^2$이며, 측정된 소모 전력은 1.8V 전원 전압 및 1GS/s 동작속도에서 594mW이다.

• 대한전자공학회논문지SD
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• 제43권5호
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• pp.54-63
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• 2006

본 논문에서는 4세대 이동 통신 시스템에서 요구되는 사양을 위해, 해상도, 동작속도, 칩 면적 및 소모 전력을 최적화한 14b 100MS/s 0.18um CMOS ADC를 제안한다. 제안하는 ADC는 동작 모델 시뮬레이션을 통해 최적화된 구조를 분석 및 검증하여 3단 파이프라인 구조로 설계하였으며, Nyquist 입력에서도 14 비트 수준의 유효비트 수를 가지는 광대역 저잡음 SHA 회로를 기반으로 하고, MDAC에 사용되는 커패시터의 소자 부정합에 의한 영향을 최소화하기 위하여 3차원 완전 대칭 구조를 갖는 레이아웃 기법을 적용하였다. 또한, 100MS/s의 동작 속도에서 6 비트의 해상도와 소면적을 필요로 하는 최종단의 flash ADC는 오픈 루프 오프셋 샘플링 및 인터폴레이션 기법을 사용하였다. 제안하는 시제품 ADC는 SMIC 0.18um CMOS 공정으로 제작되었으며, 측정된 DNL과 INL은 14비트 해상도에서 각각 1.03LSB, 5.47LSB 수준을 보이며, 100MS/s의 샘플링 속도에서 SNDR 및 SFDR이 각각 59dB, 72dB의 동적 성능을 보여준다. 시제품 ADC의 칩 면적은 $3.4mm^2$이며 소모 전력은 1.8V 전원전압에서 145mW이다.

• 한국전기전자재료학회논문지
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• 제18권4호
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• pp.285-296
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• 2005

Reduced pressure chemical vapor deposition technology has been used to study SiGe heterostructure epitaxy and device issues, including SiGe relaxed buffers, proper control of Ge component and crystalline defects, two dimensional delta doping, and their influence on electrical properties of devices. From experiments, 2D profiles of B and P presented FWHM of 5 nm and 20 nm, respectively, and doses in 5×10/sup 11/ ∼ 3×10/sup 14/ ㎝/sup -2/ range. The results could be employed to fabricate SiGe/Si heterostructure field effect transistors with both Schottky contact and MOS structure for gate electrodes. I-V characteristics of 2D P-doped HFETs revealed normal behavior except the detrimental effect of crystalline defects created at SiGe/Si interfaces due to stress relaxation. On the contrary, sharp B-doping technology resulted in significant improvement in DC performance by 20-30 ％ in transconductance and short channel effect of SiGe HMOS. High peak concentration and mobility in 2D-doped SiGe heterostructures accompanied by remarkable improvements of electrical property illustrate feasible use for nano-sale FETs and integrated circuits for radio frequency wireless communication in particular.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.130-130
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• 2011

최근 반도체 메모리 산업의 발전과 동시에 발생되는 문제들을 극복하기 위한 새로운 기술들이 요구되고 있다. DRAM (dynamic random access memory) 의 경우, 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 단채널 효과에 의한 누설전류와 소비전력의 증가 등이 문제가 되고 있다. 하나의 캐패시터와 하나의 트랜지스터로 구성된 기존의 DRAM은, 소자의 집적화가 진행 되어 가면서 정보저장 능력이 감소하는 것을 개선하기 위해, 복잡한 구조의 캐패시터 영역을 요구한다. 이에 반해 하나의 트랜지스터로 구성되어 있는 1T-DRAM의 경우, 캐패시터 영역이 없는 구조적인 이점과, SOI (silicon-on-insulator) 구조의 기판을 사용함으로써 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 그리고 기존 CMOS (complementary metal oxide semiconductor) 공정과의 호환성이 장점이다. 또한 새로운 물질 혹은 구조를 적용하여, 개선된 전기적 특성을 통해 1T-DRAM의 메모리 특성을 향상 시킬 수 있다. 본 연구에서는, SOI와 SGOI (silicon-germanium-on-insulator) 및 sSOI (strained-si-on-insulator) 기판을 사용한 MOSFET을 통해, strain 효과에 의한 전기적 특성 및 메모리 특성을 평가 하였다. 그 결과 strained-Si층과 relaxed-SiGe층간의 tensile strain에 의한 캐리어 이동도의 증가를 통해, 개선된 전기적 특성 및 메모리 특성을 확인하였다. 또한 채널층의 결함이 적은 sSOI 기판을 사용한 1T-DRAM에서 가장 뛰어난 특성을 보였다.