• 대한전기학회논문지:시스템및제어부문D
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• 제54권4호
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권11호
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• pp.768-775
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• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.529-532
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• 2000

This paper addresses how to be connected with end-to-end shortcut using ATM Switched Virtual Connection (SVC) in ATM-based Multi-Protocol Label Switching (MPLS) Networks. Without additionally existing ATM Ships-in-the-Night (SIN) mode, when the stream is continuously transmitted at the same destination with the lapse of determined aging time, the connection is changed with end-to-end shortcut connection using ATM signaling. An ATM direct short circuit is performed an IP and ATM effective integration. An ATM shortcut has a number of advantages, like higher throughput, shorter end-to-end delay, reduced router load, better utilization of L2 Quality of Service (QoS) capabilities, and route optimization. In particular between other MPLS domains, this can be efficiently improved the performance of networks.

• Journal of Radiation Protection and Research
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• 제32권3호
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• pp.117-122
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• 2007

지속적인 하수 발생량의 증가와 시설 부지비용의 상승효과로 인해 하수처리시설 중 가장 많은 면적을 차지하고 있는 침전조의 효율향상이 중요한 문제로 부각되고 있다. 본 연구에서는 선행연구로 수행한 최종 침전조 구조의 최적화를 위한 CFD(computational fluid dynamics) 모델링 결과를 실험적으로 검증하기 위해, 방사성추적자를 이용하여 정류벽 설치 유무에 따른 침전조 유동분포 변화를 측정하였다. 실제 하수처리장 침전조 설계제원을 바탕으로 수리학적 상사(1/21)를 고려하여 침전조 모형장치를 제작($L{\times}W{\times}H:2.6{\times}0.4{\times}0.2m$)하였으며, 방사성추적자로 Tc-99m 약 $30{\sim}40\;mCi$를 사용하였다. 실험결과, 최종 침전조 내부에 정류벽을 설치함으로써 바닥으로의 강한 밀도류와 출구 방향으로의 슬러지 휩쓸림 현상이 감소되었으며, 슬러지의 침전영역(settling zone)이 증가됨을 방사성추적자를 이용하여 성공적으로 가시화하여 확인하였다. 또한 정류벽 설치로 인하여 단락류가 전체 유출수에서 차지하는 부분이 48 %에서 32 %로 현저히 감소하고, 이의 슬러지 평균체재시간 또한 940 sec에서 810 sec로 감소되는 유동특성을 정량적으로 분석할 수 있었다 이는 선행연구로 실시한 CFD 모델을 이용 침전조 최적설계 조건도출 연구와 일치하는 결과로서, 방사성추적자 기술이 신규로 침전조를 설계할 때나 기존 시설의 성능개선을 위한 구조변경 후 이의 검증을 위해 중요한 자료로 활용될 수 있음을 확인하였다.