• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.11
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• pp.768-775
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• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.529-532
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• 2000

This paper addresses how to be connected with end-to-end shortcut using ATM Switched Virtual Connection (SVC) in ATM-based Multi-Protocol Label Switching (MPLS) Networks. Without additionally existing ATM Ships-in-the-Night (SIN) mode, when the stream is continuously transmitted at the same destination with the lapse of determined aging time, the connection is changed with end-to-end shortcut connection using ATM signaling. An ATM direct short circuit is performed an IP and ATM effective integration. An ATM shortcut has a number of advantages, like higher throughput, shorter end-to-end delay, reduced router load, better utilization of L2 Quality of Service (QoS) capabilities, and route optimization. In particular between other MPLS domains, this can be efficiently improved the performance of networks.

• Journal of Radiation Protection and Research
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• v.32 no.3
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• pp.117-122
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• 2007

The hydrodynamic behaviors of the clarifier with an interior baffle in a wastewater treatment plant was investigated by using a radiotracer $^{99m}Tc$(30 40 mCi) to verify the results of CFD(computational fluid dynamics) modelling in the previous study. The clarifier model was manufactured with consideration to the hydraulic similarity(1/21) of a real plant($L{\times}W{\times}H:2.6{\times}0.4{\times}0.2m$). By installation of an interior baffle to the clarifier, the strong density current at the bottom of the clarifier decreased substantially and increased the area of sludge settling zone, which were visualized successfully from the radiotracer experiment. Also the portion of short circuit stream changed from 48 % to 32 % and the mean residence time of sludge decreased from 940 sec to 810 sec, which corresponds to the results of CFD modelling. As a result, it is anticipated that radiotracer technology can be used as an important tool for designing new wastewater treatment plants and verifying their performances after structural modifications.