• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.86-90
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• 1992

We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.805-811
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• 2012

In this paper, movement of conduction path has been analyzed for electron distribution in the channel of double gate(DG) MOSFET. The analytical potential distribution model of Poisson equation, validated in previous researches, has been used to analyze transport characteristics. DGMOSFETs have the adventage to be able to reduce short channel effects due to improvement for controllability of current by two gate voltages. Since short channel effects have been occurred in subthreshold region including threshold region, the analysis of transport characteristics in subthreshold region is very important. Also transport characteristics have been influenced on the deviation of electron distribution and conduction path. In this study, the influence of electron distribution on conduction path has been analyzed according to intensity and distribution of doping and channel dimension.

• Journal of IKEEE
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• v.13 no.2
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• pp.126-131
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• 2009

To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.508-517
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• 2014

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1399-1404
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• 2015

This paper analyzed the phenomenon of drain induced barrier lowering(DIBL) for the ratio of channel length vs. thickness of asymmetric double gate(DG) MOSFET. DIBL, the important secondary effect, is occurred for short channel MOSFET in which drain voltage influences on potential barrier height of source, and significantly affects on transistor characteristics such as threshold voltage movement. The series potential distribution is derived from Poisson's equation to analyze DIBL, and threshold voltage is defined by top gate voltage of asymmetric DGMOSFET in case the off current is 10^-7 A/m. Since asymmetric DGMOSFET has the advantage that channel length and channel thickness can significantly minimize, and short channel effects reduce, DIBL is investigated for the ratio of channel length vs. thickness in this study. As a results, DIBL is greatly influenced by the ratio of channel length vs. thickness. We also know DIBL is greatly changed for bottom gate voltage, top/bottom gate oxide thickness and channel doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2267-2272
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• 2012

This study has presented the analysis of subthreshold swings based on scaling theory for double gate MOSFET. To solve the analytical potential distribution of Poisson's equation, we use Gaussian function to charge distribution. The scaling theory has been used to analyze short channel effect such as subthreshold swing degradation. These scaling factors for gate length, oxide thickness and channel thickness has been modified with the general scaling theory to include effects of double gates. We know subthreshold swing degradation is rapidly reduced when scaling factor of gate length is half of general scaling factor, and parameters such as projected range and standard projected deviation have greatly influenced on subthreshold swings.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.53-58
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• 1991

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

• Journal of information and communication convergence engineering
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• v.5 no.3
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• pp.229-232
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• 2007

This paper investigates on the use of constant-amplitude zero-autocorrelation (CAZAC) sequence for channel estimation in multiple-input multiple-output (MIMO) system over indoor wireless channel. Since the symbol-length of the conventional 4-phase CAZAC sequence is short, there is a limitation to use it for MIMO system in multipath environments. An algorithm which generates longer CAZAC sequences is proposed to overcome that problem. Flexible symbol-length of 4-phase CAZAC sequences can be made by the proposed algorithm. Therefore appropriate symbol-length of CAZAC sequences could be utilized as preambles in accordance with the number of transmit antennas and channel condition. The effect of the number of CAZAC sequences for channel estimation is presented in terms of mean square error (MSE).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1196-1202
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• 2013

This paper have analyzed the change of breakdown voltage for channel doping concentration and device parameters of double gate(DG) MOSFET using two dimensional potential model. The low breakdown voltage becomes the obstacle of power device operation, and breakdown voltage decreases seriously by the short channel effects derived from scaled down device in the case of DGMOSFET. The two dimensional analytical potential distribution derived from Poisson's equation have been used to analyze the breakdown voltage for device parameters such as channel length, channel thickness, gate oxide thickness and channel doping concentration. Resultly, we could observe the breakdown voltage has greatly influenced on device dimensional parameters as well as channel doping concentration, especially the shape of Gaussian function used as channel doping concentration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.103-112
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• 2005

In this paper, in order to derive the current-voltage characteristics of n-AlGaN/GaN HEMTs with the piezoelectric and spontaneous polarizations, we suggested analytical solutions for the two-dimensional Poisson equation in the AlGaN and GaN regions by taking into account the longitudinal field variation, field-dependent mobility, and the continuity condition of the channel current flowing in the quantum well. Obtained expressions for long and short channel devices would be applicable to the entire operating regions in a unified manner. Simulation results show that the drain saturation current increases and the cutoff voltage decreases as drain voltage increases. Compared with the conventional models, the present model seems to provide more reasonable explanation for the drain-induced threshold voltage roll-off and the channel length modulation effect.