• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.11
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• pp.572-576
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• 2006

As the increasing of capacity and technology of power facilities, rotating machines such as turbine generators and water turbines are getting higher at capacity but smaller in size. Thus the monitoring and diagnosis of generators for fault detection and protection has attracted intensive interest. Most of electrical faults of rotating machines appear in their windings. In case of an after-fault in high capacity rotating machines, the recovering cost is usually very expensive and additional time is necessary for returning in a normal situation. In this paper, the magnetic flux patterns in air-gap of a generator under various fault states as well as a normal state are simulated by a conventional FEM tool. These results are successfully applied to detection and diagnosis of the short-circuit condition in rotor windings of a high capacity generator.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1074-1084
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• 2015

These days, the widespread use of sensitive loads and distributed generators makes the solid-state circuit breaker (SSCB) an essential component in power circuits to achieve a high power quality for AC Grids. In traditional AC SSCB using SCRs, some auxiliary mechanical devices are required to make the reclosing operation possible before fault recovery. However, the proposed AC SSCB can break quickly and then be reclosed without auxiliary mechanical devices even during the short-circuit fault. Moreover, its fault current breaking time is short and its SSCB reclosing operation is fast. This results in a reduction of the economic losses due to fault currents and power outages. Through simulations and experiments on short-circuit faults, the performance characteristics of the proposed AC SSCB are verified. A design guideline is also suggested to apply the proposed AC SSCB to various AC grids.

• Progress in Superconductivity and Cryogenics
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• v.23 no.3
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• pp.51-54
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• 2021

The DC system has less power loss compared to the AC system because there is no influence of frequency and dielectric loss. However, the zero-crossing point of the current is not detected in the event of a short circuit fault, and it is difficult to interruption due to the large fault current that occurs during the opening, so the reliability of the DC breaker is required. As a solution to this, an LC resonance DC circuit breaker combined a superconducting element has been proposed. This is a method of limiting the fault current, which rises rapidly in case of a short circuit fault, with the quench resistance of the superconducting element, and interruption the fault current passing through the zero-crossing point through LC resonance. The superconducting current limiting element combined to the DC circuit breaker plays an important role in reducing the electrical burden of the circuit breaker. However, at the beginning of a short circuit fault, superconducting devices also have a large electrical burden due to large fault currents, which can destroy the element. In this paper, the reactor is connected to the source side of the circuit using PSCAD/EMTDC. After that, the change of the fault current according to the reactor capacity and the electrical burden of the superconducting element were confirmed through simulation. As a result, it was confirmed that the interruption time was delayed as the capacity of the reactor connected to the source side increased, but peak of the fault current decreased, the zero-crossing point generation time was shortened, and the electrical burden of the superconducting element decreased.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.700-702
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• 2005

The most electrical apparatus should be able to withstand short-time current and peak current during a specified short time until circuit breakers have interrupted fault current. It defines the short-time withstand ability of electric a apparatus to be remain for a time interval under high fault current conditions. It is specified by both dynamic ability and thermal capability. KERI(Korea Electrotechlology Research Institute) recently constructed the new short-time current and low voltage short circuit testing facilities. This paper shows short- circuit calculation of transformer and describes high current measuring system, and evaluate the result of short-time withstand test used in $3{\phi}$ 90MVA short-time current testing facilities.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.1000-1003
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• 2012

The superconducting fault current limiter (SFCL) can quickly limit the fault current shortly after the short circuit occurs and recover the superconducting state after the fault removes and plays a role in compensating the voltage sag of the sound feeder adjacent to the fault feeder as well as the fault current limiting operation of the fault feeder. Especially, the flux-lock type SFCL with an isolated transformer, which consists of two parallel connected coils on an iron core and the isolated transformer connected in series with one of two coils, has different voltage sag compensating and current limiting characteristics due to the winding direction and the inductance ratio of two coils. The current limiting and the voltage sag compensating characteristics of a SFCL using a transformer winding were analyzed. Through the analysis on the short-circuit tests results considering the winding direction of two coils, the SFCL designed with the additive polarity winding has shown the higher limited fault current than the SFCL designed with the subtractive polarity winding. It could be confirmed that the higher fault current limitation of the SFCL could be contributed to the higher load voltage sag compensation.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.167-178
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• 2010

To diagnose a stator winding fault caused by a short-circuited turn in a permanent magnet synchronous motor (PMSM), an on-line based fault detecting scheme during motor operation is presented. The proposed scheme is based on monitoring the second-order harmonic components in q-axis current obtained through the harmonic analysis and a winding fault is detected by comparing these components with those in normal conditions. The linear interpolation method is employed to determine harmonic data in arbitrary normal operating conditions. To verify the effectiveness of the proposed fault detecting scheme, a test motor to allow inter-turn short in the stator winding has been built. The entire control system including harmonic analysis algorithm and fault detecting algorithm is implemented using DSP TMS320F28335. The proposed scheme does not require any additional hardware and can effectively detect a fault during motor operation so long as the steady-state condition is satisfied.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.115-116
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• 2006

Since the discovery of the high-temperature superconductors, many researches have been performed for the practical applications of superconductivity technologies in various fields. As results, significant progress has been achieved. Especially, Superconducting Fault Current Limiter (SFCL) offers an attractive means to limit fault current in power systems. The SFCLS, in contrast to current limiting reactors or high impedance transformers, are capable of limiting short circuit currents without adding considerable voltage drop and energy loss to power systems during normal operation. Under fault conditions, a resistance is automatically inserted into the power grid to limit the peak short-circuit current by transition from the superconducting state to the normal state, the quench. The advantages, like fail safe operation and quick recovery, make SFCL very attractive, especially for rapidly growing power systems with higher short-circuit capacities. In order to verify the effectiveness of the SFCL, in this paper, the analysis of fault current and voltage stability assessment in a sample distribution system and a transmission system are performed by the PSCAD/EMTDC based simulation method. Through the simulation, the advantage of SFCL application is shown, and the effective parameters of the SFCL are also recommended for both distribution and transmission systems. A resistive type component of SFCL is adopted in the analysis. The simulation results demonstrate not only the effectiveness of the proposed simulation scheme but also SFCL parameter assessment technique.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.4
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• pp.210-215
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• 2013

This paper analyze the bus voltage sags in the power distribution system with a small scale cogeneration system when the superconducting fault current limiter was introduced. Among the solutions to decrease the short-circuit current considering the locations of the small scale cogeneration system, the superconducting fault current limiter (SFCL) has been announced as one of the promising methods to reduce the fault current because the installation of the small scale cogeneration system which increases the short-circuit current. According to the application locations of the small scale cogeneration system in a power distribution system, it has caused the variations of voltage sag and duration which depends on the change of the short-circuit current, which can make the operation of the protective device deviate from its original set value when the fault occurs. To investigate the voltage sag when a SFCL was applied into a power distribution system where the small scale cogeneration system was introduced into various locations, the SFCL, small scale cogeneration system, and power system are modeled using PSCAD/EMTDC. In this paper, the effects on voltage sags are assessed when the SFCL is installed in power distribution system with various locations of the small scale cogeneration system.