• Journal of the Korea Society for Simulation
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• v.26 no.1
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• pp.69-75
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• 2017

An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.9
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• pp.401-408
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• 2006

In a multi-sensor multi-target tracking systems, the local sensors have the role of tracking the target and transferring the measurements to the fusion center. The measurements from the same target can arrive out of sequence called the out-of-sequence measurements(OOSMs). Out-of-sequence measurements can arise at the fusion center due to communication delay and varying preprocessing time for different sensor platforms. In general, the track fusion occurs to enhance the tracking performance of the sensors using the measurements from the sensors at the fusion center. The target informations can wive at the fusion center with the clutter informations in cluttered environment. In this paper, the OOSM update step with MPDA(Most Probable Data Association) is introduced and tested in several cases with the various clutter density through the Monte Carlo simulation. The performance of the MPDA with OOSM update step is compared with the existing NN, PDA, and PDA-AI for the air target tracking in cluttered and out-of-sequence measurement environment. Simulation results show that MPDA with the OOSM has compatible root mean square errors with out-of-sequence PDA-AI filter and the MPDA is sufficient to be used in out-of-sequence environment.

• IE interfaces
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• v.18 no.2
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• pp.136-147
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• 2005

This paper introduces a simulation study regarding the operation of the Painted Body Storage (PBS) in an automobile factory. In the paint shop of the factory, same colored bodies are grouped together in order to increase the effectiveness of process, for example decrease the loss of cleaning the painting-gun when the color of body changes from one to another. However the production of automobiles in the assembly shop is a typical example of the mixed model assembly production. Therefore PBS locates between the paint shop and the assembly shop for control the input sequence of bodies to the assembly shop, and it enables to meet the smoothing requirement of assembly sequence. There are highly restricted constraints on the assembly sequence in a assembly shop. Those are spacing restriction and smoothing restriction. If such restrictions are violated, conveyor-stop or utility work will be necessary. Thus the major objective of PBS is to control the assembly sequence in a way to meet the two restrictions. In this paper a case study of PBS in an automotive factory is introduced. The storage/retrieval algorithms are suggested and the proposed system is verified using simulation models. Sensitivity analysis for operating factors is also conducted.

• Proceedings of the KWS Conference
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• 2004.05a
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• pp.18-20
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• 2004

This study is to find the optimal work plan of robot welding in the subassembly process of shipbuilding and to verify the found solution through 3-D simulation. The optimal work plan was established by evenly distributing the work amount to each stage and finding the shortest work sequence. The shortest work sequence was found by using the genetic algorithm. The result was compared with the practically adopted case and verified through the 3-D simulation.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.31-40
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• 2005

In this study, we study measurement of wafer processing throughput and sequence simulation of single wafer type for wafer cleaning equipments that were used for etching, cleaning and polishing of wafer. Based on finite state machine, simulation model was built with identification of robot's status according to scheduling algorithm. Moreover, through performance of simulation as above, throughput per hour of cleaning equipment was measured. By the simulation method that are proposed in this paper, we could measure the wafer throughput per hour according to recipe and robot motion speed, and find optimal recipe and moving sequence of robot that maximize the throughput.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.155-163
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• 2007

In Ad Hoc Networks, a connection breaks due to the irregular movement of mobile nodes and the inherent characteristics of the wireless medium such as the interference and the multi-path fading. AODV, a typical on-demand routing protocol in Ad Hoc networks, uses Destination sequence numbering for loop-free, but it may cause RREQ broadcast storm problem. This paper proposes AODV_ods that does not need destination sequence number, in routing message and routing table without routing loop. To show the effectiveness of the proposed scheme, we performed extensive simulation with NS-2. The simulation results show that the proposed ADOV_ods efficiently uses wireless bandwidth compare to the original AODV. Finally AODV ods reduces the routing overhead, end to end delay and increases the overall packet delivery ratio.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Journal of Information Technology Services
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• v.9 no.2
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• pp.163-177
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• 2010

In this paper, we consider a channel ordering problem that seeks to maximize the service quality in mobile radio communication systems. If a base station receives a connection request from a mobile user, one of the empty channels belonging to the base station is assigned to the mobile user. In case multiple empty channels are available, we can choose one that incurs least interference with other channels assigned to adjacent base stations. However, note that a pair of channels that are not separated enough generates interference only if both channels are assigned to mobile users. That is, interference between channels may vary depending on the channel assignment sequence for each base station and on the distribution of mobile users. To find a channel assignment sequence that seems to generate minimum interference, we develop an optimization model considering various scenarios of mobile user distribution. Simulation results show that channel assignment sequence determined by the scenario based optimization model significantly reduces the interference provided that scenarios and interference cost are properly generated.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.2
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• pp.62-68
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• 2013

The dynamic voltage restorer (DVR) is an effective protection device for wind turbine generators based on doubly-fed induction generator (DFIG) that is operated under unbalanced voltage dip conditions. The compensating voltages of the DVR depend on the voltage dips and on the influence of the zero sequence component. The zero sequence component results in high insulation costs and asymmetry in terminal voltages. This paper proposes the use of a proportional-resonant controller in stationary reference frames for controlling zero sequence components in the DVR to protect the DFIG during unbalanced voltage dips. To enhance the proposed control method, a comparison is carried out between two cases: with and without using the control of a zero sequence component. Simulation results are presented to verify the effectiveness of the proposed control method by using the Psim simulation program.

• Genomics & Informatics
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• v.6 no.2
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• pp.72-76
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• 2008

Hypoxia-inducible factor $1{\alpha}\;(HIF1{\alpha})$ is a transcription factor that plays a key role in the adaptation of cells to low oxygen stress and oxygen homeostasis. The oxygen-dependent degradation (ODD) domain of $HIF1{\alpha}$ is responsible for the negative regulation of $HIF1{\alpha}$ in normoxia. The interactions of the $HIF1{\alpha}$ ODD domain with partner proteins such as von Hippel-Lindau tumor suppressor (pVHL) and p53 are mediated by two sequence motifs, the N- and C-terminal ODD(NODD and CODD). Multiple sequence alignment with $HIF1{\alpha}$ homologs from human, monkey, pig, rat, mouse, chicken, frog, and zebrafish has demonstrated that the NODD and CODD motifs have noticeably high conservation of the primary sequence across different species and isoforms. In this study, we carried out molecular dynamics simulation of the structure of the $HIF1{\alpha}$ CODD motif in complex with the p53 DNA-binding domain (DBD). The structure reveals specific functional roles of highly conserved residues in the CODD sequence motif of $HIF1{\alpha}$ for the recognition of p53.