• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.2
• /
• pp.56-62
• /
• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.2
• /
• pp.485-490
• /
• 2010

We propose the equivalent circuit model including all parasitic components in input gate of sense amplifier of DDI DRAM with butting contact structure. We analysed the effect of parasitic schottky diode by using the proposed model in the operation of sense amplifier. The cause of single side fail and the temperature dependence of fail rate in DDI DRAM are due to creation of the parasitic schottky diode in input gate of sense amplifier. The parasitic schottky diode cause the voltage drop in input gate, and result in decreasing noise margin of sense amplifier. therefore single side fail rate increase.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.5
• /
• pp.777-784
• /
• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

• Proceedings of the KIEE Conference
• /
• 1988.11a
• /
• pp.159-163
• /
• 1988

The purpose of this paper is to investigate the effects of alpha particles on the memory circuits such as a sense amplifier and bit lines. Sense amplifiers column alpha particle hits have been simulated for a mega bit DRAM using SPICE, a circuit simulation program. The energy of alpha particle and the substrate concentration are found to strongly influence the likehood of soft errors. Our results may be useful for the designing of alpha particle immune sense amplifiers.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.2
• /
• pp.39-46
• /
• 2012

The newly designed sense amplifier in this paper has rail-to-rail input range achieving low power consumption. Reducing static power consumption generated due to DC path to ground is key element for low power consumption in this paper. The proposed sense amplifier performs power-saving operation using negative feedback circuit that controls the current flow with the newly added PMOS input terminal. As a simulation result, the proposed sense amplifier consumed about over 50 % efficiency of the average power consumed by the typical Rail-to-Rail sense amplifier.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.2
• /
• pp.67-75
• /
• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.433-436
• /
• 1998

Hot carrier induceed the performance degradation of sense amplifier circuit in DRAM has been measured and analyzed using 0.8.mu.m CMOS process. Simulation and experimental results show that the degradation of the MOS devices affects the decrease of the half-Vcc, voltage gain and the increase of the sensing voltage gain and the increase of the sensing voltage. The dominant degradation mechanism is the capacitance imblance in the bit-line pair. We carried out the spice simulation to investigate the degradation of the sense amplifier circuit.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.979-982
• /
• 2003

Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1559-1562
• /
• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.4
• /
• pp.1-9
• /
• 2002

The distribution characteristics of data retention time for DRAM was studied in connection with the probability distribution of the cell parameters. Using the cell parameters and the transient characteristics of cell node voltage, data retention time was investigated. The activation energy for dielectric layer growth on cell capacitance, the recombination trap energy for leakage current in the junction depletion region, and the sensitivity characteristics of sense amplifier were used as the random variables to perform the Monte Carlo simulation, and the probability distributions of cell parameters and distribution characteristics of cumulative failure bit on data retention time in DRAM cells were calculated. we found that the sensitivity characteristics of sense amplifier strongly affected on the tail bit distribution of data retention time.