• 한국정보통신학회논문지
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• 제12권7호
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• pp.1227-1234
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• 2008

본 논문에서는 자동차 전장용 Power IC, 디스플레이 구동 칩, CMOS 이미지 센서 등의 응용분야에서 필요로 하는 동기식 256-bit OTP(one-time programmable) 메모리를 설계하였다. 동기식 256-bit OTP 메모리의 셀은 고전압 차단 트랜지스터 없이 안티퓨즈인 NMOS 커패시터와 액세스 트랜지스터로 구성되어 있다. 기존의 3종류의 전원 전압을 사용하는 대신 로직 전원 전압인 VDD(=1.5V)와 외부 프로그램 전압인 VPPE(=5.5V)를 사용하므로 부가적인 차단 트랜지스터의 게이트 바이어스 전압 회로를 제거하였다. 그리고 프로그램시 전류 제한 없이 전압 구동을 하는 경우 안티퓨즈의 ON 저항 값과 공정 변동에 따라 프로그램 할 셀의 부하 전류가 증가한다. 그러므로 프로그램 전압은 VPP 전원 선에서의 저항성 전압 감소로 인해 상대적으로 증가하는 문제가 있다. 그래서 본 논문에서는 전압 구동 대신 전류 구동방식을 사용하여 OTP 셀을 프로그램 할 때 일정한 부하전류가 흐르게 한다. 그래서 웨이퍼 측정 결과 VPPE 전압은 5.9V에서 5.5V로 0.4V 정도 낮출 수 있도록 하였다. 또한 기존의 전류 감지 증폭기 대신 Clocked 인버터를 사용한 감지 증폭기를 사용하여 회로를 단순화시켰다. 동기식 256-bit OTP IP는 매그나칩 반도체 $0.13{\mu}m$ 공정을 이용하여 설계하였으며, 레이아웃 면적은 $298.4{\times}3.14{\mu}m2$이다.

• 한국통신학회논문지
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• 제16권2호
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• pp.145-154
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• 1991

본 논문에서는 데이터의 저장과 판독은 일반 SRAM과 같고 명령과 탐색을 수행하는 8비트 $\times16$ 워드 연상메모리(CAM: Content Addressable Memory)의 알고리즘과 하드웨어를 제시하였다. 설계된 연상메모리 칩은 5개의 기능별 블록(연상메모리 셀 어레이. 어드레스 디코더, 어드레스 인코터, 데이터 셀럭터, 감지 증폭기)으로 나누어서 설계하고 논리 및 회로 검증을 마친 후 3 um CMOS N Well공정을 이용하여 칩을 제작하였다

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.1-10
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• 2007

In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.173-179
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• 2002

We propose a novel sensing circuit for 2T-2MTJ MRAM that can be used for high speed synchronous operation. Proposed bit-line sense amplifier detects small voltage difference in bit-lines and develops it into rail-to-rail swing while maintaining small voltage difference on TMR cells. It is small enough to fit into each column that the whole data array on selected word line are activated as in DRAMs for high-speed read-out by changing column addresses only. We designed a 256Kb read-only MRAM in a $0.35\mu\textrm{m}$ logic technology to verify the new sensing scheme. Simulation result shows a 25ns RAS access time and a cycle time shorter than 10 ns.

• 한국소음진동공학회논문집
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• 제15권2호
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• pp.239-247
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• 2005

This paper deals with the development of a contact-type counting device using a piezoelectric polymer film as a sensor. The piezoelectric and vibration characteristics of the film under a bending vibration were investigated theoretically and experimentally. A counting device, which includes filters, an amplifier, an analog-digital converter, and a display, was designed and fabricated. The performance of the piezoelectric polymer sensor was evaluated in the sense of the responses to contact force, contact frequency, and contact speed. The life and the temperature effect were also investigated for the piezoelectric film sensor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.561-562
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• 2006

This paper presents an SRAM which uses the technique to equalize the internal cell node by adding an NMOS transistor. Accordingly, the write driver operates rapidly in a differential current of bit lines, and the operation speed of SRAM improves. An SRAM was implemented with a memory cell, a sense amplifier and a write driver. The SRAM obtained the performance of 18% power reduction and improvement of 56% operation speed. And Power delay product was reduced with 63%. The proposed SRAM was designed based on a 0.35um 1P4M CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.302-308
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• 2011

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flip-flop based on a sense amplifier and a photon-emitting device. This method can be used even with deep-submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 ${\mu}m$ CMOS process.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.417-420
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• 2007

A 12k-bit SRAM has been developed for line memory of system-on-glass (SoG) with lowtemperature poly-silicon (LTPS) thin film transistor (TFT). For accurate sensing even with the large variation and mismatches in the characteristics of LTPS TFT, mismatch immune sense amplifier is developed. The SRAM shows 30ns read access time with 7V supply voltage while dissipating 4.05mW and 1.75mW for write and read operation, respectively

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.154-158
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• 2005

In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.