• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.150-153
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• 2015

An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.522-529
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• 2007

A semidynamic frequency divide-by-1.5 MMIC comprises a tunable polyphase filter, tunable image-rejection mixer, and a static divide-by-2 in the feedback path. Wideband suppression of unwanted tones is achieved by employing a tunable image-rejection mixer and a tunable single-stage polyphase filter. Implemented in GaInP/GaAs HBT technology, the divide-by-1.5 MMIC operates over the input frequency range of 4.5 to 9.2 GHz with better than -20 dBc suppressions of $1/3{\times}f_{in}\;and\;f_{in}$ tones, while dissipating 29 mA from 4.1 V supply.