JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

An Energy-Efficient 64-bit Prefix Adder based on Semidynamic and Bypassing Structures

  • Hwang, Jaemin (Department of Computer Science and Engineering, Chungnam National University) ;
  • Choi, Seongrim (Department of Computer Science and Engineering, Chungnam National University) ;
  • Nam, Byeong-Gyu (Department of Computer Science and Engineering, Chungnam National University)
  • Received : 2014.10.30
  • Accepted : 2015.01.21
  • Published : 2015.02.28
Download PDF
⟨ Previous Next ⟩

Abstract

An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.

Keywords

References

  1. Y.-S. Wang et al., "A 1.2V 6.4GHz 181ps 64-bit CD Domino Adder with DLL Measurement Technique," IEEE Int. Symp. on Circuits and Systems, pp. 1423-1426, 2011.
  2. S. Mathew et al., "A 4-GHz 130-nm Address Generation Unit With 32-bit Sparse-Tree Adder Core," IEEE J. Solid-State Circuits, 38(5), pp. 689-695, 2003. https://doi.org/10.1109/JSSC.2003.810056
  3. S. Choi et al., "Energy-efficient static sparse-tree adder based on MUX-less bypassing architecture," Electron. Lett., 50(25), pp. 1914-1915, 2014. https://doi.org/10.1049/el.2014.1639