• Journal of the Semiconductor & Display Technology
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• v.12 no.3
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• pp.7-12
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• 2013

Ni-CNT(Carbon Nanotube) composite coatings is were formed by electrodeposition and their physical properties were investigated with variations of CNT content(1, 3, 6. 9 g/L) in the electrolyte solution, while the current density and electroplating time were fixed respectively at $6A/dm^2$ and 90 min.. With increasing CNT content from 1 to 9 g/L, incorporated CNTs into the composite coating were limited from 4.65 wt.% to 7.38 wt.%. Microhardness and contact angle values were increased with increasing CNT content of upto 3 g/L. With increasing the CNT content further, physical properties were degraded due to agglomeration, poor adhesion of CNTs to Ni matrix and thus rough surfaces. Optimum electroplating conditions were found to be the CNT content of 3 g/L, current density of 6 A/dm2 and electroplating time of 90 min.

• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.153-155
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• 2010

실리콘 태양전지의 pn 접합 계면특성을 조사하기 위해서 p형 실리콘 기판 위에 전기로를 이용한 $POCl_3$ 공정을 통하여 n형의 불순물을 주입하여 pn접합을 만들었다. n형 불순물의 확산되어 들어가는 공정시간이 길고 공정온도가 높을수록 면저항은 줄어들었다. n형 불순물의 주입이 많아질수록 pn 접합 계면에서의 전자친화도가 줄어들면서 면저항은 감소되었다고 할 수 있다. n형 반도체의 페르미레벨이 높아지면서 공핍층도 생기지만 n형 불순물이 많아지면서 공핍층의 폭은 점점 좁아지고 쇼키 장벽의 높이도 낮아지면서 자유전자와 홀 쌍의 이동이 쉽게 이루어지게 되었다. n형의 불순물 확산공정시간이 긴 태양전지 셀에서 F.F. 계수가 높게 나타났으며, 효율도 높게 나타났다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.112-115
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• 2003

Sub-90nm급 high speed 소자를 위해서는 extension영역의 shallow junction과 sheet 저항의 감소가 필수적이다. 일반적으로 기생저항은 channel저항의 약 10-20%정도를 차지하도록 제작되므로, 이를 최소화하여 optimize하기 위해서는 기생저항에 대한 성분 분리와 이들이 가지는 저항값에 대한 정량적 계산이 이루어져야 한다. 이에 본 논문은 calibration된 TCAD simulation을 통해 90nm급 Tr. 에서 각 영역의 저항성분을 계산, 평가하는 방법을 제시한다. 이 결과, 특히, extension영역의 표면-accumulation부분이 가장 개선이 있어야 할 부분으로 분석되었으며, 이 저항은 gate하부에 존재하는 extension으로부터 발if되는 측면 doping의 tail영역으로 인해 형성되는 것으로,doping의 abruptness가 가장 중요한 factor인 것으로 판단된다.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.87-91
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• 2019

As a highly conductive and transparent electrode, ITO/Ag/ITO multilayers are fabricated using an in-line sputtering method. Optimal thickness conditions have been investigated in terms of the optical transmittance and the electrical conductance. Considering the optical properties, in this study, the experimental characteristics are analyzed based on theoretical phenomena, and they are compared with the simulated results. The simulations are based on the finite-difference-time-domain (FDTD) method in solving linear Maxwell equations. Consequently, the results showed that ITO/Ag/ITO multilayer structures with respective thicknesses of 39.2 nm/10.7 nm/39.2 nm are most suitable with an average transmittance of about 87% calculated for wavelengths ranging from 400-800 nm and a sheet resistance of about $7.1{\Omega}/{\square}$.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.810-812
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• 2009

반도체 소자공정에서 균일한 두께의 금속박막을 증착하는 것은 매우 중요하다. sputtering 방법의 경우, 증착조건을 조절하기 쉽고, 특히 대형 기판을 사용하여 제조할 경우 박막의 두께 등 박막 특성의 균일화를 기하는데 용이한 장점을 가지고 있다. 하지만, 기존의 기판고정식 sputtering 장비로 증착한 Al 박막은 증착 시에 가해지는 전력의 크기에 따라 그 특성의 변화를 생긴다. 이런 전력의 크기에 따른 Al 박막의 reflectance, sheet resistance 그리고 uniformity 등을 분석하여 Al 박막의 우수한 증착 조건을 알 수 있었다.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2034-2036
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• 2005

Four Point Probe 방법을 이용한 반도체 wafer의 면저항 측정을 위하여 single configuration 기술을 적용한 회로를 설계 제작하였으며, 제작된 FPP장치의 면저항 측정범위는 $10{\sim}3000{\Omega}/sq.$ 이고 측정의 정확도는 약 0.5%이하이다.

• Journal of Sensor Science and Technology
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• v.33 no.1
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• pp.24-29
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• 2024

Inkjet printing technology is used to mass-produce displays and electrochemical sensors by dropping tens of pico-liters or less of specific-purpose ink through nozzles, just as ink is sprayed and printed on paper. Unlike the deposition method for vaporizing material in a vacuum, inkjet printing technology can be used for processing even under general atmospheric pressure and has a cost advantage because the material is dissolved in a solvent and used in the form of ink. In addition, because it can only be printed on the desired part, masks are not required. However, a technical shortcoming is the difficulty for commercialization, such as uniformity for forming the thickness and coffee ring effect. As sizes of devices decrease, the need to print electrodes with precision, thinness, and uniformity increases. In this study, we improved the printing and processing conditions to form a homogeneous electrode using Ag ink (DGP-45LT-15C) and applied this for patterning to fabricate a heat sensor. Upon the application of voltage to the heat sensor, the model with an extended width exhibited superior heat performance. However, in terms of sheet resistance, the model yielded an equivalent value of 21.6 Ω/□ compared to the ITO.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.193-198
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• 2007

The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.34-41
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• 1984

MOEN/MO double layer which is to be used It)r the RMOS (refractory metal oxide semiconductor) gate material has been fabricated by means of low temperature reactive sputtering in N2 and Ar mixture. Good Mo2N film was obtained in the volumetric mixture of Ar:N2=95:5. The sheet resistance of the fabricated Mo7N film was about 1.20 - 1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film, and this would enable to improve the operational speed of devices fabricated with this material. When PSG (phosphorus silicate glass) was used as impurity diffusion source for the source and drain of the RMOSFET in the N2 atmosphere at about 110$0^{\circ}C$, the Mo2N was reduced to Mo resulting in much smaller sheet resistance of about 0.38 ohm/square. The threshold voltage of the RMOSFET fabricated in our experiment was - 1.5 V, and both depletion and enhancement mode RMOSFETs could be obtained.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.