• Title/Summary/Keyword: Semiconductor manufacturing

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Fabrication of Multi-crystalline Silicon Solar Cell by using Wafer Adhesion Texturing Method (웨이퍼 접착 텍스쳐링 방식을 이용한 다결정 실리콘 태양전지 제조)

  • Yoon, Seok-Il;Roh, Si-Cheol;Choi, Jeong- Ho;Jung, Jong-Dae;Seo, Hwa-Il
    • Journal of the Semiconductor & Display Technology
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    • v.15 no.4
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    • pp.67-72
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    • 2016
  • In this study, the texturing and the emitter formation processes were carried out with the wafer adhesion method to increase the productivity and reduce the production cost of the multi-crystalline silicon solar cell. After fabricating $156{\times}156mm$ solar cell according to the wafer adhesion method, the operation characteristics were analyzed and compared with those of the solar cell fabricated by the standard process method. In the case of a solar cell formed by the wafer adhesion method, it showed Jsc of $32.87mA/cm^2$, Voc of 0.612V, FF of 78.04% and efficiency of 15.71% respectively. The efficiency of the solar cell formed by the wafer adhesion method was 0.1% higher than that of the solar cell formed by the standard method. In addition, the productivity of the texturing and the emitter formation processes is expected to be approximately doubled. Therefore, it is expected that the manufacturing cost of the multi-crystalline solar cell can be reduced due to the improved productivity compared with the standard process.

Phase Error Accumulation Methodology for On-chip Cell Characterization (온 칩 셀 특성을 위한 위상 오차 축적 기법)

  • Kang, Chang-Soo;Im, In-Ho
    • 전자공학회논문지 IE
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    • v.48 no.2
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    • pp.6-11
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    • 2011
  • This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

Design of Variable Gain Receiver Front-end with Wide Gain Variable Range and Low Power Consumption for 5.25 GHz (5.25 GHz에서 넓은 이득 제어 범위를 갖는 저전력 가변 이득 프론트-엔드 설계)

  • Ahn, Young-Bin;Jeong, Ji-Chai
    • Journal of IKEEE
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    • v.14 no.4
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    • pp.257-262
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    • 2010
  • We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

Interfacial Microstructure and Electrical Properties of $Al_2O_3/Si$ Interface of Mono-crystalline Silicon Solar Cells (단결정 실리콘 태양전지에서 후열처리에 따른 $Al_2O_3/Si$ 계면조직의 특성 변화)

  • Paek, Sin Hye;Kim, In Seob;Cheon, Joo Yong;Chun, Hui Gon
    • Journal of the Semiconductor & Display Technology
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    • v.12 no.3
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    • pp.41-46
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    • 2013
  • Efficient and inexpensive solar cells are necessary for photo-voltaic to be widely adopted for mainstream electricity generation. For this to occur, the recombination losses of charge carriers (i.e. electrons or holes) must be minimized using a surface passivation technique suitable for manufacturing. Recently it has been shown that aluminum oxide thin films are negatively charged dielectrics that provide excellent surface passivation of silicon solar cells to attract positive-charged holes. Especially aluminum oxide thin film is a quite suitable passivation on the rear side of p-type silicon solar cells. This paper, it demonstrate the interfacial microstructure and electrical properties of mono-crystalline silicon surface passivated by $Al_2O_3$ films during firing process as applied for screen-printed solar cells. The first task is a comparison of the interfacial microstructure and chemical bonds of PECVD $Al_2O_3$ and of PEALD $Al_2O_3$ films for the surface passivation of silicon. The second is to study electrical properties of double-stacked layers of PEALD $Al_2O_3$/PECVD SiN films after firing process in the temperature range of $650{\sim}950^{\circ}C$.

Development of a High speed Actuator for electric performance testing System of ceramic chips (세라믹칩 전기적 성능검사 시스템을 위한 고속구동 액튜에이터 개발)

  • Bae, Jin-Ho;Kim, Sung-Gaun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.4
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    • pp.1509-1514
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    • 2011
  • The core of IT products, electronic components, especially the MLCC, chip inductors, chip Varistors and so on. In order to test the electrical characteristics of the chip using the Reno-pin contact test method has been used. In current chips, mass production of semiconductor manufacturing processes, high-speed production test for the chip speed up, precision is required. But Vibration displacement is a very short, so in order to overcome these shortcomings, the displacement amplification to design the structure has been actively studied. In this paper, a building structure with a flexible hinge was designed amplification instrument, semiconductor chip industry in the performance test and inspection equipment to measure the electrical characteristics of high speed linear actuators Reno-Pin using system was developed.

Implementation of Logic Gates Using Organic Thin Film Transistor for Gate Driver of Flexible Organic Light-Emitting Diode Displays (유기 박막 트랜지스터를 이용한 유연한 디스플레이의 게이트 드라이버용 로직 게이트 구현)

  • Cho, Seung-Il;Mizukami, Makoto
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.1
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    • pp.87-96
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    • 2019
  • Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

A study on the mold opening stroke according to the control method of the injection molding machine (사출성형기의 속도제어 방식에 따른 형개거리에 관한 연구)

  • Jung, Hyun-Suk;Lee, Chun-Kyu
    • Design & Manufacturing
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    • v.15 no.3
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    • pp.56-61
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    • 2021
  • The increase in automation facilities in the injection molding industry is a very important process control item. The most important item when constructing an unmanned machine using a take-out robot is the "mold opening stroke" of the mold. The injection molding machine control method is divided into hydraulic type and electric type, and there have been few studies on the mold opening distance according to the control method. In this study, the correlation was confirmed by increasing the injection speed to 20, 50, 80, and 100% for the three types of hydraulic control method, open loop and close loop, and electric control method. Through the experiment, the following results were obtained. (1) It can be seen that the reproducibility is excellent with the electric, close loop, and open loop control methods. (2) When the injection speed is set to 50%, the mold opening distance is 263.10~263.27 mm, which is the most reproducible. (3) As a result of ANOVA, both injection speed and mold opening distance showed a significant difference in the hydraulic control method (p<0.05), but it was verified through experiments that there was no significant difference in the electric control method. Based on these results, when electric control is selected rather than hydraulic control, the reproducibility of the mold opening distance is excellent, so it is thought that the taking-out robot can take the object out of the mold more safely.

A Study on Flow Analysis according to the Cause of Gas Leakage in the Specialty Gas Supply Device for Semiconductors (반도체용 특수가스 공급장치 내부에서의 가스누출 원인에 따른 유동해석에 관한 연구)

  • Kim, Jung-Duck;Kwon, Ki-sun;Rhim, Jong-Guk;Yang, Won-Baek
    • Journal of the Korean Institute of Gas
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    • v.25 no.2
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    • pp.42-51
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    • 2021
  • Facilities that supply specialty gases used in semiconductor manufacturing mainly handles with hazardous and dangerous substances with flammable, toxic, and corrosive properties, and gas cabinets are mainly used as such supply facilities. The effects of the supply facilities were analyzed for each leak through the rupture disk in the gas cabinet and a leak where the leak hole. In this case, gas leaked to the outside depending on the leak area. It is a factor that creates a risk depending on the concentration of the leaked gas. Depending on the risk of leakage, all measures such as safe operation procedures should be reviewed again.

A Simulation-based Optimization for Scheduling in a Fab: Comparative Study on Different Sampling Methods (시뮬레이션 기반 반도체 포토공정 스케줄링을 위한 샘플링 대안 비교)

  • Hyunjung Yoon;Gwanguk Han;Bonggwon Kang;Soondo Hong
    • Journal of the Korea Society for Simulation
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    • v.32 no.3
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    • pp.67-74
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    • 2023
  • A semiconductor fabrication facility(FAB) is one of the most capital-intensive and large-scale manufacturing systems which operate under complex and uncertain constraints through hundreds of fabrication steps. To improve fab performance with intuitive scheduling, practitioners have used weighted-sum scheduling. Since the determination of weights in the scheduling significantly affects fab performance, they often rely on simulation-based decision making for obtaining optimal weights. However, a large-scale and high-fidelity simulation generally is time-intensive to evaluate with an exhaustive search. In this study, we investigated three sampling methods (i.e., Optimal latin hypercube sampling(OLHS), Genetic algorithm(GA), and Decision tree based sequential search(DSS)) for the optimization. Our simulation experiments demonstrate that: (1) three methods outperform greedy heuristics in performance metrics; (2) GA and DSS can be promising tools to accelerate the decision-making process.

MAGICal Synthesis: Memory-Efficient Approach for Generative Semiconductor Package Image Construction (MAGICal Synthesis: 반도체 패키지 이미지 생성을 위한 메모리 효율적 접근법)

  • Yunbin Chang;Wonyong Choi;Keejun Han
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.4
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    • pp.69-78
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    • 2023
  • With the rapid growth of artificial intelligence, the demand for semiconductors is enormously increasing everywhere. To ensure the manufacturing quality and quantity simultaneously, the importance of automatic defect detection during the packaging process has been re-visited by adapting various deep learning-based methodologies into automatic packaging defect inspection. Deep learning (DL) models require a large amount of data for training, but due to the nature of the semiconductor industry where security is important, sharing and labeling of relevant data is challenging, making it difficult for model training. In this study, we propose a new framework for securing sufficient data for DL models with fewer computing resources through a divide-and-conquer approach. The proposed method divides high-resolution images into pre-defined sub-regions and assigns conditional labels to each region, then trains individual sub-regions and boundaries with boundary loss inducing the globally coherent and seamless images. Afterwards, full-size image is reconstructed by combining divided sub-regions. The experimental results show that the images obtained through this research have high efficiency, consistency, quality, and generality.