• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.343-346
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• 2003

A systematic study of Cu CMP in terms of the effect of slurry chemicals(oxidizer, corrosion inhibitor, complexing agent) on the process characteristics has been performed. In acidic media, a corrosion inhibitor, benzotriazole(BTA) and tolytriazol(TTA) was used to control the removal rate and avoid isotropic etching. When complexing agent is added with $H_2O_2$ 2wt% in the slurry, a corrosion rate was presented very good. Most of in, it was appeared that BTA is possible to be replaced by TTA. The tartaric acid was distinguished for the effect among complexing agents. n we apply this results to copper CMP process, it is thought that we will be able to obtain better yield.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.6
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• pp.519-522
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• 2008

As industry of a semiconductor and LCD industry have been rapidly growing, precision technologies of machining such as etching and 3D measurement are required. Stylus has been important measuring method in traditional manufacturing process. However, its disadvantages are low measuring speed and damage possibility at contacting point. To overcome mentioned disadvantage, non-contacting measurement method is needed such as PMP(Phase Measuring Profilometry), WSI(white scanning interferometer) and Confocal Profilometry. Among above 3 well-known methods, WSI started to be applied to FPD(flat panel display) manufacturing process. Even though it overcomes 21t ambiguity of PMP method and can measure objects which has specular surface, the measuring speed and vibration coming from manufacturing machine are one of main issue to apply full automatic total inspection. In this study, We develop high speed WSI system and algorithm to reduce unknown noise. The developing WSI and algorithm are implemented to measure 3D surface of wafer. Experimental results revealed that the proposed system and algorithm are able to measure 3D surface profile of wafer with a good precision and high speed.

• Transactions on Electrical and Electronic Materials
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• v.4 no.6
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• pp.28-31
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• 2003

Copper CMP in terms of the effect of slurry chemicals (oxidizer, corrosion inhibitor, complexing agent) on the process characteristics has been performed. Corrosion inhibitors, benzotriazole (BTA) and tolytriazol (TTA) were used to control the removal rate and avoid isotropic etching. When complexing agent is added with H$_2$O$_2$ 2 wt% in the slurry, the corrosion rate was presented very well. In the case of complexing agent, it was estimated that the proper concentration is 1 wt%, because the addition of tartaric acid to alumina slurry causes low pH and the slurry dispersion stability become unstable. There was not much change of the removal rate. It was assumed that BTA 0.05 wt% is suitable. Most of all, it was appeared that BTA is possible to be replaced by TTA. TTA was distinguished for the effect among complexing agents.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.105-110
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• 2024

Scanning probe microscopy (SPM) has become an indispensable tool in efforts to develop the next generation of nanoelectronic devices, given its achievable nanometer spatial resolution and highly versatile ability to measure a variety of properties. Recently a new scanning probe microscope was developed to overcome the tip degradation problem of the classic SPM. The main advantage of this new method, called Reverse tip sample (RTS) SPM, is that a single tip can be replaced by a chip containing hundreds to thousands of tips. Generally for use in RTS SPM, pyramid-shaped diamond tips are made by molding on a silicon substrate. Combining RTS SPM with Scanning spreading resistance microscopy (SSRM) using the diamond tip offers the potential to perform 3D profiling of semiconductor materials. However, damage frequently occurs to the completed tips because of the complex manufacturing process. In this work, we design, fabricate, and evaluate an RTS tip chip prototype to simplify the complex manufacturing process, prevent tip damage, and shorten manufacturing time.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.237.1-237.1
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• 2014

Etching is one of the most important steps in semiconductor manufacturing. In etch process control a critical task is to stop the etch process when the layer to be etched has been removed. If the etch process is allowed to continue beyond this time, the material gets over-etched and the lower layer is partially removed. On the other hand if the etch process is stopped too early, part of the layer to be etched still remains, called under-etched. Endpoint detection (EPD) is used to detect the most accurate time to stop the etch process in order to avoid over or under etch. The goal of this research is to develop a hardware and software system for EPD. The hardware consists of an Optical Plasma Monitor (OPM) sensor which is used to continuously monitor the plasma optical emission intensity during the etch process. The OPM software was developed to acquire and analyze the data to perform EPD. Our EPD algorithm is based on the following theory. As the etch process starts the plasma generated in the vacuum is added with the by-products from the etch reactions on the layer being etched. As the endpoint reaches and the layer gets completely removed the plasma constituents change gradually changing the optical intensity of the plasma. Although the change in optical intensity is not apparent, the difference in the plasma constituents when the endpoint has reached leaves a unique signature in the data gathered. Though not detectable in time domain, this signature could be obscured in the frequency spectrum of the data. By filtering and analysis of the changes in the frequency spectrum before and after the endpoint we could extract this signature. In order to do that, first, the EPD algorithm converts the time series signal into frequency domain. Next the noise in the frequency spectrum is removed to look for the useful frequency constituents of the data. Once these useful frequencies have been selected, they are monitored continuously in time and using a sub-algorithm the endpoint is detected when significant changes are observed in those signals. The experiment consisted of three kinds of etch processes; ashing, SiO2 on Si etch and metal on Si etch to develop and evaluate the EPD system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.440-440
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• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.93-101
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• 2002

We have proposed and fabricated two lateral type field emission diodes, poly-Si emitter by utilizing the local oxidation of silicon (LOCOS) and GaN emitter using metal organic chemical vapor deposition (MOCVD) process. The fabricated poly-Si diode exhibited excellent electrical characteristics such as a very low turn-on voltage of 2 V and a high emission current of $300{\;}\bu\textrm{A}/tip$ at the anode-to-cathode voltage of 25 V. These superior field emission characteristics was speculated as a result of strong surface modification inducing a quasi-negative electron affinity and the increase of emitting sites due to local sharp protrusions by an appropriate activation treatment. In respect, two kinds of procedures were proposed for the fabrication of the lateral type GaN emitter: a selective etching method with electron cyclotron resonance-reactive ion etching (ECR-RIE) or a simple selective growth by utilizing $Si_3N_4$ film as a masking layer. The fabricated device using the ECR-RIE exhibited electrical characteristics such as a turn-on voltage of 35 V for $7\bu\textrm{m}$ gap and an emission current of~580 nA/l0tips at anode-to-cathode voltage of 100 V. These new field emission characteristics of GaN tips are believed to be due to a low electron affinity as well as the shorter inter-electrode distance. Compared to lateral type GaN field emission diode using ECR-RIE, re-grown GaN emitters shows sharper shape tips and shorter inter-electrode distance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.263-267
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• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.20-25
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• 2010

An integrated Mach-Zehnder interferometric sensor operating at 632.8 nm was designed and fabricated by the technology of planar rib waveguides. Rib waveguide based on silica system ($SiO_2-SiO_xN_y-SiO_2$) was geometrically designed to have single mode operation and high sensitivity. It was structured by semiconductor fabrication processes such as thin film deposition, photolithography, and RIE (Reactive Ion Etching). With the power observation, propagation loss measurement by cut-back method showed about 4.82 dB/cm for rib waveguides. Additionally the chromium mask process for an etch stop was employed to solve the core damaging problem in patterning the sensing zone on the chip. Refractive index measurement of water/ethanol mixture with this device finally showed a sensitivity of about $\pi$/($4.04{\times}10^{-3}$).