• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.87-89
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• 2006

This paper proposes a sense amplifier with non-volatile memory in order to improve the image quality of LCD by enhancing the matching of the driving voltages between the panel and driver. The sense amplifier having a wide sensing margin and fast response adjusts LCD driver voltage of display driver. The CSTN-LCD with the sense amplifier results improved image quality than that with conventional 6 bit column driver without it.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.335-339
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• 2003

This Paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard 0.25$\mu\textrm{m}$ CMOS technology and is shown to deliver 100mW output Power to load with 41％ power added efficiency(PAE) from a 2.5V supply.

• 대한의용생체공학회:의공학회지
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• 제2권1호
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• pp.55-64
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• 1981

The important parameters of DC amplifier, which is widely use4 for the medical and engineering fields, are input offset voltage and temperature drift. Chopping amplifier reduces approximately 10% the parameters changing than monolithic operational amplifier. In this study, a chopping amplifier with semiconductor chopper is designed and tested, this chopper is realized by CMOS analog switch and timing circuits. The test results approve that designed amplifier is suitable for precision instrument DC amplifier.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.278-283
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• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.

• 한국광학회지
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• 제13권1호
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• pp.84-87
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• 2002

SOA (Semiconductor Optical Amplifier)의 inverter 원리를 응용하여 RZ 형식의 전광 XOR논리소자가 5 Gb/s 속도에서 처음으론 구현되었다. 먼저 Boolean AB와 Boolean AB가 실험적으로 구현되었으며 전광 XOR논리소자를 만들기 위해서 AB와 AB를 합하여 XOR의 Boolean 값인 AB+AB의 특성이 얻어졌다.

• Journal of the Optical Society of Korea
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• 제19권3호
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• pp.222-227
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• 2015

We propose a new and potentially integrable scheme for the realization of an all-optical binary full adder employing two XOR gates, two AND gates, and one OR gate. The XOR gate is realized using a Mach-Zehnder interferometer (MZI) based on a semiconductor optical amplifier (SOA). The AND and OR gates are based on the nonlinear properties of a semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a carry bit from the previous less-significant bit order position. In our proposed design, we achieve extinction ratios for Sum and Carry output signals of 10 dB and 12 dB respectively. Successful operation of the system is demonstrated at 10 Gb/s with return-to-zero modulated signals.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.113-117
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• 2003

This paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard $0.25{\mu}m$ CMOS technology and is shown to deliver 100mW output power to load with 41% power added efficiency(PAE) from a 2.5V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.67-75
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• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• 반도체디스플레이기술학회지
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• 제16권4호
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• pp.63-67
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• 2017

In this study, We developed a simple and low cost capacitive pressure mapping sensor and microcontroller-base lock-in amplifier array. We developed capacitive type pressure mapping sensor by forming the electrode and adhesives on plastic films using only the printing process, and the finishing the process by bonding the two films. Lock-in amplifier array was based on a general purpose microcontroller and had only a charge amplifier as analog circuits. In this study, a $10{\times}10$ capacitive type pressure mapping sensor and lock-in amplifier array was fabricated and its characteristics were analyzed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.195-198
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• 2000

A CMOS power amplifier for wireless home networks is designed using 0.2sum 1-poly 5-metal standard CMOS technology and simulation results are presented. The power amplifier provides maximum output power of 16.5dBm to a 50-Ohm load at 2.450Hz and dissipates 220mW of dc power from a single 2.5-V supply. The designed CMOS power amplifier has power control range of 20dB and an overall power-added efficiency of 17%