• ETRI Journal
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• 제43권5호
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• pp.900-908
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• 2021

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛² and 197 ㎛², respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

• 대한전자공학회논문지
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• 제23권6호
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• pp.929-935
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• 1986

In this paper, we describe the physical modelling and numerical aspects of a program called PRECISE(Program for Efficient Calculation of Impurity Profile in Semiconductor by Elimination) which calcualtes a two-dimensional impurity profile in silicon due to diffusion and ion implantation steps. The PRECISE enables rapid prediction of the two-dimensional impurity profile near the mask edge-or the bird's beak during the local oxidation process. This has been developed by modifying the existing one-dimentional simulator, DIFSIM(DIFfusion SIMulator to include models for arsenic diffusion and emitter dip effect which were found out to agree fairly well with the xperimental data.

• 한국산학기술학회논문지
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• 제4권3호
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• pp.317-321
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• 2003

우리가 타자기로 글을 쓸 때는 먹지리본을 햄머가 가격하여 종이 위에 글씨 형태의 먹이 묻는 원리로 진행된다. 이러한 원리를 미세 패터닝에 응용하여, 해머 역할을 하는 Nd-YAG 레이저로 유리기판/ 100 ㎚ Cr(먹지)// 실리콘기판(종이)구조의 적층물에 조사시켜 Cr이 실리콘기판 위에 전사됨으로써 미세 패터닝이 가능한지 확인하였다. 제안된 미세 패터닝은 TeraBit/in²급 고밀도 정보저장 또는 반도체 공정의 생산성 향상을 위해 응용이 가능하다. 선폭 50 ㎛급 레이저를 주사속도 200과 1500 ㎜/s Q-스위치 조건을 10,000-50,000 Hz로 변화시키며 마킹을 실시한 결과 Cr의 전사는 진행되지 않았으나, 최종적으로 입사 선폭의 33％ 이하로 마킹이 가능하여 비싼 광학계를 가진 레이저를 대치하여 보다 정밀한 마킹이 가능함을 확인하였다.

• 펄프종이기술
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• 제36권1호
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• pp.1-8
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• 2004

One of the most frequently used method for measurement of the degree of sizing (viz., hydrophobicity) is the Stockigt test. However, the Stockigt test was influenced by various factors such as dropping height, dropping amount, dropping speed and viewing angle. The resultant data of the sizing degree on the same specimen also varied according to different testers. Thus, the Stockigt test should be modified to be regarded as a highly reliable and reproducible standard method. For modifying the Stockigt test, it was required to quantify red coloration by reaction between 1％ ferric chloride and 2％ ammonium thiocyante during Stockigt testing. The cameras capturing the serial images during the red coloration process were the CMOS (Complementary Metal Oxide Semiconductor)-type and CCD (Charge Coupled Device)-type cameras. For measurement based on KS M 7025, the CCD-type camera must be used due to its high resolution, and on the other hand, for measurement based on Tappi Useful Method 429, the CMOS-type camera may be used owing to its low resolution. It was needed to covert the RGB values of a droplet image into HSV(Hue, Saturation, and Value) values because the human eyes are much closer to HSV than RGB. Among HSV values, the Hue value was accepted as the most reliable index consistent with the red coloration process by excluding the surrounding conditions such as light, tester's movement etc.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.175-183
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• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.307-312
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• 2014

We present a full finite element analysis for plasma discharge in etching process of semiconductor circuit. The charge transport equations of hydrodynamic diffusion-drift model and the electric field equation were numerically solved in a fully coupled system by using a standard finite element procedure for transient analysis. The proposed method was applied to a real plasma reactor in order to characterize the plasma sheath that is closely related to the yield of the etching process. Throughout the plasma discharge analysis, the base electrode of reactor was tested and modified for improving the uniformity around the wafer edge. The experiment and numerical results were examined along with SEM data of etching quality. The feasibility and usefulness of the proposed method was shown by both numerical and experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• Tribology and Lubricants
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• 제40권2호
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• pp.67-70
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• 2024

Chemical mechanical planarization (CMP) is an essential process for ensuring high integration when manufacturing semiconductor devices. CMP mainly requires the use of polyurethane-based polishing pads as an ultraprecise process to achieve mechanical material removal and the required chemical reactions. A diamond disk performs pad conditioning to remove processing residues on the pad surface and maintain sufficient surface roughness during CMP. However, the diamond grits attached to the disk cause uneven wear of the pad, leading to the poor uniformity of material removal during CMP. This study investigates the pad wear rate profile according to the swing motion of the conditioner during swing-arm-type CMP conditioning using deep learning. During conditioning, the motion of the swing arm is independently controlled in eight zones of the same pad radius. The experiment includes six swingmotion conditions to obtain actual data on the pad wear rate profile, and deep learning learns the pad wear rate profile obtained in the experiment. The absolute average error rate between the experimental values and learning results is 0.01%. This finding confirms that the experimental results can be well represented by learning. Pad wear rate profile prediction using the learning results reveals good agreement between the predicted and experimental values.

• 한국정보통신학회논문지
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• 제25권3호
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• pp.433-439
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• 2021

본 논문에서는 사물인터넷을 이용하여 조선소의 작업장 단위로 센서네트워크를 구축하는 방안을 제시한다. 여기서는 조선소에서 가장 흔한 용접 작업장에서 조선블록을 통신매체로 활용하여 작업자의 위치, 용접 진행률, 작업 시간 등의 정보를 LoRa와 전력선통신을 이용하여 서버로 전송한다. 이와 같은 데이터통신을 위하여 유도성 커플러와 복합통신용 모뎀을 제작하여 와이어피더와 핀지그에 설치하여 센서네트워크를 구축하였다. 시험 결과, 제시된 시스템은 약 98% 이상의 데이터 전송 성공률과 작업자 위치 인식 성공률을 가지는 것으로 나타났다. 또한, 현장에서 발생된 작업 데이터는 실시간 기록과 디스플레이가 가능함을 공정관리시스템 플랫폼을 통하여 확인하였다. 제시된 시스템은 미래형 스마트 조선소 구축을 통한 우리나라 조선산업의 경쟁력 강화를 위한 단초가 될 것으로 사료된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.232-239
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• 2010

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.