• Journal of Korean Institute of Industrial Engineers
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• v.27 no.4
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• pp.394-405
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• 2001

Since most real-world application data involve continuous-valued attributes, properly addressing the discretization process for constructing a decision tree is an important problem. A continuous-valued attribute is typically discretized during decision tree generation by partitioning its range into two intervals recursively. In this paper, by removing the restriction to the binary discretization, we present a hybrid multi-interval discretization algorithm for discretizing the range of continuous-valued attribute into multiple intervals. On the basis of experiment using semiconductor etching machine, it has been verified that our discretization algorithm constructs a more efficient incremental decision tree compared to previously proposed discretization algorithms.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.227-234
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• 2014

A transceiver for a high-speed inductive-coupling link is proposed. The bi-phase modulation (BPM) signaling scheme is used due to its good noise immunity. The transmitter utilizes a complementary switching method to remove glitches in transmitted data. To increase the timing margin on the receiver side, an integrating receiver with a pre-charging equalizer is employed. The proposed transceiver was implemented via a 130-nm CMOS process. The measured timing window for a $10^{-12}$ bit error rate (BER) at 1.8 Gb/s was 0.33 UI.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.23-28
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• 2017

Non-volatile RAM (NVRAM) provides many opportunities to improve the performance of computing devices. In this paper, we present an approach that reduces the user-perceived latency of browsers by using NVRAM. To this end, we first analyze the browser launch process, and then employ several techniques that improve the performance of each step by using NVRAM. Specially, we focus on minimizing the launch time of browser by 1) prefetching the block sequence required for browser launch, 2) caching the web resources in the fast NVRAM, and 3) reusing the displayed bitmap data in the frame buffer. Through implementation, we show that our scheme significantly reduces the launch time of browsers.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1676-1681
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• 2006

We report on Organic Vapor Phase Deposition $(OVPD^{(R)})$ an innovative deposition technology for organic light emitting device (OLED) and organic semiconductor manufacturing. The combination of $OVPD^{(R)}$ with Close Coupled Showerhead (CCS) technology results in manufacturing equipment with vast potential for cost effective manufacturing of OLED displays commercially competitive to LCD. The actual $OVPD^{(R)}$ equipment concept and design is discussed: Computational Fluid Dynamic (CFD) modeling is compared with experimental results proving the excellent controllability of the deposition process. Further other production relevant deposition properties are being reviewed e.g. high deposition rates and high organic material utilization efficiency of the $OVPD^{(R)}$ - Technology. Data from devices made by $OVPD^{(R)}$ show comparable/ superior performance to those fabricated with conventional vacuum thermal evaporation (VTE) techniques. An outlook on further potentials of $OVPD^{(R)}$ with respect to enabling advanced organic device structures is given.

• Electrical & Electronic Materials
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• v.7 no.2
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• pp.157-164
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• 1994

DRAM(Dynamic Random Access Memory)은 반도체 소자중 가장 대표적인 기억소자로, switch역활을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고집적화에 용이하다는 이점을 바탕으로, supercomputer에서 가전제품 및 산업기기에 이르기 까지 널리 이용되어왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기시장 진입을 위하여 초기에 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락등이 심하여, 시한내 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성도 가지고 있다. 이러한 관점때문에 새로운 DRAM기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-micron이하의 DRAM세대로 갈수록 그에 대한 신기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화/저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 대한 breakthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇가지 중요한 item을 설정하여 논의해 보기로 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.112-117
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• 2016

This paper presents a half-rate current-integrating DFE receiver with sub-unit interval (sub-UI) inter-symbol interference (ISI) cancellation. By having a single additional DFE tap in each data path, the proposed DFE receiver can minimize BER degradation due to input pattern dependency and feedback tap latency problems in conventional current-integrating DFE receivers. The proposed DFE receiver was designed and fabricated in a 45 nm CMOS process, whose measurement results indicated that the BER bathtub width is increased from 0.235 UI to 0.315 UI (34% improvement) at $10^{-12}$ BER level.

• Journal of Korean Society for Quality Management
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• v.38 no.3
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• pp.354-362
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• 2010

This paper presents a non-linear control chart based on support vector machine regression (SVM-R) to improve the accuracy of fault detection of cyclic signals. The proposed algorithm consists of the following two steps. First, the center line of the control chart is constructed by using SVM-R. Second, we calculate control limits by variances that are estimated by perpendicular and normal line of the center line. For performance evaluation, we apply proposed algorithm to the industrial data of the chemical vapor deposition process which is one of the semiconductor processes. The proposed method has better fault detection performance than other existing method

• Proceedings of the Korea Technology Innovation Society Conference
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• 2017.11a
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• pp.763-777
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• 2017

기술집약적 산업의 급격한 기술혁신 속도 및 환경변화에 따른 기술수명 주기의 단축, 기술간 경쟁을 통한 시장지배력의 우위를 선점하기 위해 기술융합을 통한 연구전략 수립은 중요한 이슈가 되고 있다. 최근 4차 산업혁명 기반의 반도체산업이 이러한 예이며, 이와 같은 기술집약적 산업의 기술융합이 매우 중요해짐에 따라, 관련 전략수립을 위한 다양한 방법이 시도되고 있다. 본 논문에서는 데이터 기반의 논문 특허 분석을 통해 반도체산업의 플라즈마 기술이슈의 기술융합 동향 및 특허 동향 분석과 이를 통한 특허 전략 수립 사례를 제시하고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.33-39
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• 2011

H.264 decoders usually have pipeline architecture by a macroblock or a 4 ${\times}$ 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.6-14
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• 2011

This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 ${\mu}M$ CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 ${\times}$ 4 matrix decomposition.