• 한국전기전자재료학회논문지
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• 제25권5호
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• pp.353-360
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• 2012

As semiconductor device technology continuously shrinks, low-open area etch process prevails in front-end etch process, such as contact etch as well as one cylindrical storage (OCS) etch. To eliminate over loaded wafer processing test, it is commonly performed to emply diced small coupons at stage of initiative process development. In nominal etch condition, etch responses of whole wafer test and coupon test may be regarded to provide similar results; however, optical emission spectroscopy (OES) which is frequently utilize to monitor etch chemistry inside the chamber cannot be regarded as the same, especially etch mask is not the same material with wafer chuck. In this experiment, we compared OES data acquired from two cases of etch experiments; one with coupon etch tests mounted on photoresist coated wafer and the other with coupons only on the chuck. We observed different behaviors of OES data from the two sets of experiment, and the analytical results showed that careful investigation should be taken place in OES study, especially in coupon size etch.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.135-145
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• 2011

Accurate process characterization and optimization are the first step for a successful advanced process control (APC), and they should be followed by continuous monitoring and control in order to run manufacturing processes most efficiently. In this paper, process characterization and recipe optimization methods with multiple outputs are presented in high density plasma-chemical vapor deposition (HDP-CVD) silicon dioxide deposition process. Five controllable process variables of Top $SiH_4$, Bottom $SiH_4$, $O_2$, Top RF Power, and Bottom RF Power, and two responses of interest, such as deposition rate and uniformity, are simultaneously considered employing both statistical response surface methodology (RSM) and neural networks (NNs) based genetic algorithm (GA). Statistically, two phases of experimental design was performed, and the established statistical models were optimized using performance index (PI). Artificial intelligently, NN process model with two outputs were established, and recipe synthesis was performed employing GA. Statistical RSM offers minimum numbers of experiment to build regression models and response surface models, but the analysis of the data need to satisfy underlying assumption and statistical data analysis capability. NN based-GA does not require any underlying assumption for data modeling; however, the selection of the input data for the model establishment is important for accurate model construction. Both statistical and artificial intelligent methods suggest competitive characterization and optimization results in HDP-CVD $SiO_2$ deposition process, and the NN based-GA method showed 26% uniformity improvement with 36% less $SiH_4$ gas usage yielding 20.8 ${\AA}/sec$ deposition rate.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.101-106
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• 2011

There are various methods in the flat panel display manufacture. The cost reduction effect is very big in case of using the screen printing method. The screen printing method is much used in the process of forming PDP barrier and can apply to the process of arranging the pillars for maintaining the vacuum gap of the vacuum glazing panel. The pillar which is one of the core elements for comprising vacuum glazing maintains the vacuum gap overcoming the vacuum pressure difference with the atmospheric pressure generated in vacuum glazing. At the same time, the deformation phenomenon by vacuum pressure is relived. In this paper, by using FEM about three considered in the pillar design and arrangement kinds of limiting factors, the simulation was performed. The pillar optimum arrangement method at within the maximum allowable tensile stress and heat transfer coefficients according to the arrangement try to be presented based upon the analyzed result data review and this validity tries to be verified by FEM.

• 전기전자학회논문지
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• 제28권2호
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• pp.158-167
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• 2024

본 논문에서는, 시뮬레이션 상에서 반도체 후단 공정의 프로세스를 구현하고 파이프 내부 상황을 모니터링하기 위해 전기 정전용량을 기반으로 한 U-net 모델을 적용하였다. 배관에 부착된 전극에서 측정한 정전용량 값은 U-net 네트워크 모델의 입력 데이터로 사용되며, 모델을 통해 추정한 유전율 분포를 가지고 파이프 단면을 이미지화하였다. 성능 평가를 위해 수치 시뮬레이션 얀에서 U-net 모델, FCNN(Fully-connected neural network) 모델, Newton-Raphson 방법으로 재구성한 이미지를 비교한 결과, U-net이 다른 이미지 복원 방식보다 좋은 복원 성능을 보였다.

• 한국컴퓨터정보학회논문지
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• 제25권12호
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• pp.73-82
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• 2020

반도체나 석유화학 공정과 같이 프로세스 중심의 장치 산업에서는 흔히 관측된 자료들 사이에 자기상관(Autocorrelation)이 존재하는데, 이러한 공정에 기존의 SPC(Statistical process control)를 적용하는 경우 공정의 평균 변화를 효과적으로 검출하지 못하는 문제가 발생할 수 있다. 본 논문에서는 특정 시계열 모형을 따르는 공정자료에 일정한 크기의 평균 변화가 발생할 때, 잔차는 시간의 흐름에 따라 그 평균이 달라지게 되는데, ARMA(1,1) 과정을 중심으로 평균의 변화 패턴을 소개하고, 이 결과를 바탕으로 공정의 작은 평균 변화를 검출할 수 있는 CUSUM(Cumulative sum) 관리도의 공정 자료가 갖는 시계열 모형의 형태와 관심 있는 공정 평균 변화의 폭을 고려하여 CUSUM 관리도의 설계 과정에서 필요한 참고값이 적절히 선택되어 사용되어야 함을 모의실험을 통해 확인하였다.

• 전자공학회논문지A
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• 제33A권7호
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• pp.198-204
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• 1996

Electron beam lithography is one of the importnat technologies which can delineate deep submicron patterns. REcently, electron beam lithography is being applied in delineating the critical layers of semiconductor device fabrication. In this paper, we present a development simulation program for electron beam lithography and study the development profiles of resist when resist is exposed by the electron beam. Experimentally, the development parameter of positive and negative resists are measured and the data is applied to input parameter of the simulation program. Also simulation results are compared of the process results in the view of resist profiles. As a result, for PMMA and SAL 601 resist, the trend of simulation to the values of process parameters agree with real process results very well, so that the process results can be predicted by the simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.40-45
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• 2008

We developed small molecular organic nonvolatile $4F^2$ memory cells using metal layer evaporation followed by $O_2$ plasma oxidation. Our memory cells sandwich an upper ${\alpha}$-NPD layer, Al nanocrystals surrounded by $Al_2O_3$, and a bottom ${\alpha}$-NPD layer between top and bottom electrodes. Their nonvolatile memory characteristics are excellent: the $V_{th},\;V_p$ (program), $V_e$ (erase), memory margin ($I_{on}/I_{off}$), data retention time, and erase and program endurance were 2.6 V, 5.3 V, 8.5 V, ${\approx}1.5{\times}10^2,\;1{\times}10^5s$, and $1{\times}10^3$ cycles, respectively. They also demonstrated symmetrical current versus voltage characteristics and a reversible erase and program process, indicating potential for terabit-level nonvolatile memory.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.40-45
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• 1994

The TCAD(Technology Computer Aided Design) software tool is a popular name to be able to simulate the semiconductor process and device circuit. We have developed a two-dimensional TCAD software tool included an editor, parser, each process unit, and 2D, 3D graphic routine that is Integrated Environment. The initial grid for numerical analysis is automatically generated with the geometric series that use the user default(given) line and position separated with grid interval and the nodes corresponding to each mesh point stoic the all the possible attribute. Also, we made a data structure called PIF for input or output. Methods of ion implantation in this paper arc Monte Carlo, Gaussian Pearson and Dual-Pearson. Analytical model such as Gaussian, Pearson and Dual-Pearson were considered the multilayer structure and two-dimensional tilted implantation. We simuttaneously calculated the continuity equation of impurity and point defect in diffusion simulation. Oxidation process was simulated by analytical ERFC(Complementary Error Function) model for local oxidation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.142.2-142.2
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• 2015

Plasma etch endpoint detection (EPD) of SiO2 and PR layer is demonstrated by plasma impedance monitoring in this work. Plasma etching process is the core process for making fine pattern devices in semiconductor fabrication, and the etching endpoint detection is one of the essential FDC (Fault Detection and Classification) for yield management and mass production. In general, Optical emission spectrocopy (OES) has been used to detect endpoint because OES can be a simple, non-invasive and real-time plasma monitoring tool. In OES, the trend of a few sensitive wavelengths is traced. However, in case of small-open area etch endpoint detection (ex. contact etch), it is at the boundary of the detection limit because of weak signal intensities of reaction reactants and products. Furthemore, the various materials covering the wafer such as photoresist (PR), dielectric materials, and metals make the analysis of OES signals complicated. In this study, full spectra of optical emission signals were collected and the data were analyzed by a data-mining approach, modified K-means cluster analysis. The K-means cluster analysis is modified suitably to analyze a thousand of wavelength variables from OES. This technique can improve the sensitivity of EPD for small area oxide layer etching processes: about 1.0 % oxide area. This technique is expected to be applied to various plasma monitoring applications including fault detections as well as EPD.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.1485-1488
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• 1997

The capacity of memory chip has increased vert quickly and 64MDRAM becomes main product in semiconductor manufacturing lines consists of many sequential processes, including etching process. although it needs direct sensing of wafer state for the accurae detching, it depends on indirect esnsing and sample test because of the complexity of the plasma etching. This equipment receives the inner light of etch chamber through the viewport and convets it to the voltage inetnsity. In this paper, EDP voltage signal has a new role to detect etching failure. First, we gathered data(EPD sigal, etching time and etchrate) and then analyzed the relationships between the signal variatin and the etch rate using two neural network modeling. These methods enable to predict whether ething state is good or not per wafer. For experiments, it is used High Density Inductive coupled Plasma(HDICP) ethcing equipment. Experiments and results proved to be abled to determine the etching state of wafer on-line and analyze the causes by modeling and EPD signal data.