• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.865-868
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• 2005

$Pb_{0.72}La_{0.28}TiO_3$ (PLT(28)) 박막을 sol-gel 법을 이용하여 제작한 후, 그 특성을 조사하여 ULSI DRAM 의 캐패시터 절연막으로서의 적용 가능성을 연구하였다. Sol-gel 법의 출발 물질로는 acetate계를 사용하였다. TGA-DTA 분석을 통하여 PLT(28) 박막의 sol-gel 법에 의한 공정 조건을 확립하였다. 매 coating 후 350$^{\circ}C$에서 drying 하고, 마지막으로 650$^{\circ}C$에서 annealing 하여 100% perovskite 구조를 가지는 치밀하고 crack 이 없는 PLT(28) 박막을 얻었다. Pt/Ti/SiO$_2$/Si 기판 위에 PLT(28) 박막을 형성하여 전기적 특성을 측정하였다. 그 결과 유전 상수와 누설전류밀도가 각각 936 과 1.1${\mu}$A/cm$^2$ 으로 측정되었다.

• 한국산학기술학회논문지
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• 제12권12호
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• pp.5832-5837
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• 2011

본 논문에서는 1 ${\mu}m$ CMOS 공정을 사용하여 LED 구동회로용 과열방지회로를 제안하였다. 제안하는 과열 방지회로는 $120^{\circ}C$에서 동작하며 $90^{\circ}C$에서 차단되도록 설계하였으며, 공정 오차에 따른 과열방지회로의 특성 변화가 많이 감소되었다. 세 가지 공정변화에 따른 특성 변화를 본 결과 제안하는 과열방지회로의 시뮬레이션 결과는 기존의 BJT 전류미러 방식의 과열방지회로보다 공정에 따른 온도변화가 약 7 % 줄어드는 것을 확인하였다. 또한 가상의 LED 구동회로에 연결하였을 때 과열로부터 LED 구동회로를 보호하는 것을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회논문지
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• 제24권9호
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• pp.701-709
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• 2011

In semiconductor wafer fabrication, etching is one of the most critical processes, by which a material layer is selectively removed. Because of difficulty to correct a mistake caused by over etching, it is critical that etch should be performed correctly. This paper proposes a new approach for etch endpoint detection of small open area wafers. The traditional endpoint detection technique uses a few manually selected wavelengths, which are adequate for large open areas. As the integrated circuit devices continue to shrink in geometry and increase in device density, detecting the endpoint for small open areas presents a serious challenge to process engineers. In this work, a high-resolution optical emission spectroscopy (OES) sensor is used to provide the necessary sensitivity for detecting subtle endpoint signal. Partial Least Squares (PLS) method is used to analyze the OES data which reduces dimension of the data and increases gap between classes. Support Vector Machine (SVM) is employed to detect endpoint using the data after PLS. SVM classifies normal etching state and after endpoint state. Two data sets from OES are used in training PLS and SVM. The other data sets are used to test the performance of the model. The results show that the trained PLS and SVM hybrid algorithm model detects endpoint accurately.

• 한국전기전자재료학회논문지
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• 제30권8호
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• pp.525-529
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• 2017

Molybdenum oxide ($MoO_3$) offers pivotal advantages for high optical transparency and low light reflection. Considering device fabrication, n-type $MoO_3$ semiconductor can spontaneously establish a junction with p-type Si. Since the energy bandgap of Si is 1.12 eV, a maximum photon wavelength of around 1,100 nm is required to initiate effective photoelectric reaction. However, the utilization of infrared photons is very limited for Si photonics. Hence, to enhance the Si photoelectric devices, we applied the wide energy bandgap $MoO_3$ (3.7 eV) top-layer onto Si. Using a large-scale production method, a wafer-scale $MoO_3$ device was fabricated with a highly crystalline structure. The $MoO_3/p-Si$ heterojunction device provides distinct photoresponses for long wavelength photons at 900 nm and 1,100 nm with extremely fast response times: rise time of 65.69 ms and fall time of 71.82 ms. We demonstrate the high-performing $MoO_3/p-Si$ infrared photodetector and provide a design scheme for the extension of Si for the utilization of long-wavelength light.

• 한국전기전자재료학회논문지
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• 제31권6호
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• pp.377-385
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• 2018

For the investigation of dopant profiles in implanted $Si_{1-x}Ge_x$, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in $Si_{1-x}Ge_x$ are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of $R_p$ and 1.8% deviations of ${\Delta}R_p$ owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of $R_p$ and 8.1% deviations of ${\Delta}R_p$ in the arsenic implanted $Si_{0.2}Ge_{0.8}$ layer and 8.5% deviations of $R_p$ and 38% deviations of ${\Delta}R_p$ in the $Si_{0.5}Ge_{0.5}$ layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the $Si_{1-x}Ge_x$ layer becomes more important for accurate device scaling and fabrication technologies.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• 한국전기전자재료학회논문지
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• 제20권7호
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• pp.594-599
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• 2007

[ $CulnS_2$ ] thin films were synthesized by sulfurization of Cu/In Stacked elemental layer deposited onto glass Substrates by vacuum furnace annealing at temperature $200^{\circ}C$. And structural and electrical properties were measured in order to certify optimum conditions for growth of the ternary compound semiconductor $CuInS_2$ thin films with non-stoichiometry composition. $CuInS_2$ thin film was well made at the annealed $200^{\circ}C$ of SLG/Cu/In/S stacked elemental layer which was prepared by thermal evaporator, and chemical composition of the thin film was analyzed nearly as the proportion of 1 : 1 : 2. Physical properties of the thin film were investigated at various fabrication conditions substrate temperature, annealing and temperature, annealing time by XRD, FE-SEM and Hall measurement system. The compositional deviations from the ideal chemical formula for $200^{\circ}C$ material can be conveniently described by non-molecularity$({\Delta}x=[Cu/In]-1)$ and non-stoichiometry $({\Delta}y=[{2S/(Cu+3In)}-1])$. The variation of ${\Delta}x$ would lead to the formation of equal number of donor and accepters and the films would behave like a compensated material. The ${\Delta}y$ parameter is related to the electronic defects and would determine the type of the majority charge carriers. Films with ${\Delta}y>0$ would behave as p-type material while ${\Delta}y<0$ would show n-type conductivity. At the sane time, carrier concentration, hall mobility and resistivity of the thin films was $9.10568{\times}10^{17}cm^{-3},\;312.502cm^2/V{\cdot}s\;and\;2.36{\times}10^{-2}\;{\Omega}{\cdot}cm$, respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.93-93
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• 2010

Semiconductor nanocrystal quantum dots (NQDs) have recently attracted considerable interest for use in photovoltaics. Band gaps of NQDs can be tuned over a considerable range by varying the particle size thereby allowing enhance absorption of solar spectrum. NQDs, synthesized using colloidal routes, are solution processable and promise for a large-area fabrication. Recent advancements in multiple-exciton generation in NQD solutions have afforded possible efficiency improvements. Various architectures have attempted to utilize the NQDs in photovoltaics, such as NQD-sensitized solar cell, NQD-bulk-heterojuction solar cell and etc. Here we have fabricated CdSe NQDs with the band gap of 1.8 eV to 2.1 eV on thin-layers of p-type organic crystallites (1.61 eV) to realize a donor-acceptor type heterojuction solar cell. Simple structure as it was, we could control the interface of electrode-p-layer, and n-p-layer and monitor the following efficiency changes. Specifically, surface molecules adsorbed on the NQDs were critical to enhance the carrier transfer among the n-layer where we could verify by measuring the photo-response from the NQD layers only. Further modifying the annealing temperature after the deposition of NQDs on p-layers allowed higher conversion efficiencies in the device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.9-10
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• 2010

Since the discovery of graphene by mechanical exfoliation from graphite[1], various fabrication methods are available today such as chemical exfoliation, epitaxial graphene on SiC substrates, etc. In view of industrialization, the mechanical exfoliation method may not be an option. Epitaxial graphene on SiC substrates, in this respect, is by far more practical because the method consists of conventional thermal treatments familiar to semiconductor industry. Still, the use of the SiC substrate itself, and hence the incompatibility with the Si technology, lessens the importance of this technology in its future industrialization. In this context, we have tackled the problem of forming graphene on Si substrates (GOS). Our strategy is to form an ultrathin (~80 nm) SiC layer on top of a Si substrate, and to graphitize the top SiC layers by a vacuum annealing. We have actually succeeded in forming the GOS structure [2,3,4]. Raman-scattering microscopy indicates presence of few-layer graphene (FLG) formed on our annealed SiC/Si heterostructure, with the G ($1580\;cm^{-1}$) and the G'($2700\;cm^{-1}$) bands, both related to ideal graphene, clearly observed. Presence of the D ($1350\;cm^{-1}$) band indicates presence of defects in our GOS films, whose elimination remains as a challenge in the future. To obtain qualified graphene films on Si substrate, formation of qualified SiC films is crucial in the first place, and is achieved by tuning the growth parameters into a process window[5]. With a potential for forming graphene films on large-scale Si wafers, GOS is a powerful candidate as a key technology in bringing graphene into silicon technology.