• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• 한국전기전자재료학회논문지
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• 제20권3호
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• pp.213-217
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• 2007

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 춘계학술발표대회 논문집
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• pp.116-120
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• 2011

In this paper, we studied the optimization of the screen pringting method for crystalline silicon solar cell fabrication. The 156 * 156 mm2 p-type silicon wafers with $200{\mu}m$ thickness and $0.5-3{\Omega}cm$ resistivity were used after texturing, doping, and passivation. Screen printing method is a common way to make the c-Si solar cell with low-cost and high-efficiency. We studied the optimized condition for screen printing with crystalline silicon solar cell as changing the printing direction (finger line or bus bar), finger width, and mesh angle. As a result, the screen printing with finger line direction showed higher finger height and better conversion efficiency, compared with one with bus bar direction. The experiments with various finger widths and mesh angles were also carried out. The characteristics of solar cells was obtained by measuring light current-voltage, optical microscope and electroluminescence.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.65-70
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• 2011

These days, printed electronics attract attention from electronics industry. In this paper, the fabrication of the fine patterns by Near Field Electro Spinning (NFES) was studied by using Ag ink on silicon wafer (substrate). Two types of ink, the high viscous ink Ag-200 and low viscous ink Ag-15, were used. The fine and uniform patterns were easily fabricated by using Ag-200 because jet breakup is less occurred in high viscosity solution. As increasing flow rate of solution, aspect ratio of Ag pattern decreased. And there was optimum applied voltage for fine pattern. In case of Ag-200, the optimum applied voltage was about 2.02KV. When pattern was fabricated by NFES, the pattern width and height were affected by many factors such as viscosity, flow rate of solution, applied voltage etc.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 추계학술발표대회 논문집
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• pp.40-44
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• 2011

Recent studies in crystalline silicon solar cell fabrication have been focused on high efficiency and low cost. However, the rising of the cost results in additional processes to approach high efficiency. The fabrication process also becomes complicated with additional technologies. In this paper, we studied the selective emitter formation with phosphorous paste to improve the conversion efficiency. Selective emitter formations like two-step diffusion or etch-back method require at least one more step compared in the conventional line since heavily and lightly doped area was needed to form separately.However,one-step diffusion process is the method diffusing heavily and lightly doped area at the same time only with additional screen-printing step. This study lays the foundation for the simple way to form the selective emitter.

• 반도체디스플레이기술학회지
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• 제19권1호
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• pp.73-78
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• 2020

There appears lateral capillary force in a hydrophilic flat needle employed for the fabrication of fine organic thin-film stripes, bringing in an increase of the stripe width. It also causes the stripe thickness to increase with increasing coating speed, which is hardly observed in a normal coating process. Through computational fluid dynamics (CFD) simulations, we demonstrate that the lateral capillary flow can be substantially suppressed by increasing the contact angle of the needle end. Based on the simulation results, we have coated the outer surface of the flat needle with a hydrophobic material (polytetrafluoroethylene (PTFE) with the water contact angle of 104°). Using such a hydrophobic needle, we can suppress the lateral capillary flow of an aqueous poly(3,4-ethylenedioxythiophene): poly(4-styrenesulfonate) (PEDOT:PSS) to a great extent, rendering the stripe narrow (63 ㎛ at 30 mm/s). Consequently, the stripe thickness is decreased as the coating speed increases. To demonstrate its applicability to solution-processable organic light-emitting diodes (OLEDs), we have also fabricated OLED with the fine PEDOT: PSS stripe and observed the strong light-emitting stripe with the width of about 68 ㎛.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.587-587
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• 2013

ZnS is well-known direct band gap II-VI semiconductor, and it attracts intense interest due to its excellent properties of luminescence which enable ZnS to have promising materials for optical, photonic and electronic devices. Especially, the emission wavelength of ZnS falls in the UV absorption band of most organic compoundsand biomolecules, thus it is envisaged that ZnS based devices may find applications in increasingly important fluorescence sensing. We have developed a facile and effective one-step process for the fabrication of single-crystalline and pure-wurtzite ZnS nanostructures possessing sharp band-edge emission at room-temperature having diverse length-to-width ratios. Each of nanostructures was composed of chemically pure, structurally uniform, single-crystalline, and defect-free ZnS. These features not only suppress trap or surface states emission centered at 420 nm, but also enhance UV band-edge emission centered at 327 nm, which give as-synthesized our ZnS nanostructures possible sharp UV emission at room temperature. The reaction medium consisting of mixed solvents such as hydrazine, ethylenediamine, and water as well as proper reaction time and temperature have played an important role in the crystallinity and optical properties of ZnS nanostructures. As-synthesized our ZnS nanostructures possessing sharp UV emission guarantee high potential for both fundamental research and technological applications.

• 반도체디스플레이기술학회지
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• 제8권2호
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• pp.1-10
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• 2009

This study describes the electron beam lithography pattern fabrication using the proximity effect correction. When electron beam exposes into electron beam resist, the beam tends to spread inside the substance (forward scattering). And the electron beam reflected from substrate spreads again (back scattering). These two effects influence to distribution of the energy and give rise to a proximity effect while a small pattern is generated. In this article, an electron energy distribution is modeled using Gaussian shaped beam distribution and those parameters in the model are computed to solidify the model. The proximity effect is analyzed through simulations and appropriate corrections to reducing the proximity effect are suggested. It is found that the proximate effect can be reduced by adopting schemes of dose adjustment, and the optimal dose is determined through simulations. The proposed corrected proximity effect correction is proved by experiments.

• 반도체디스플레이기술학회지
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• 제18권2호
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• pp.58-62
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• 2019

Diffractive Optical Elements(DOEs) diffracts incident light using the diffraction phenomenon of light to generate a desired diffraction image. In recent years, the use of diffraction optics, which can replace existing refractive optical elements with flat plates, has been increased by implementing various optical functions that could not be implemented in refractive optical devices and by becoming miniaturized and compacted optical elements. Direct laser lithography is typically used to effectively fabrication such a diffractive optical element in a large area with a low process cost. In this study, the process conditions for fabricating patterns of diffractive optical elements in various shapes were found using direct laser lithographic system, and optical performance evaluation was performed through fabrication.

• 반도체디스플레이기술학회지
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• 제20권3호
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• pp.32-38
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• 2021

We developed an inductively coupled plasma (ICP) etcher for GaN etching using a parallel plasma electrode source with a multifunctional chuck matched to it in order for the low power consumption and low process cost in comparison with the conventional ICP system with a helical-type plasma electrode source. The optimization process condition using it for the micro light-emitting diode (µ-LED) chip fabrication was established, which is an ICP RF power of 300 W, a chuck power of 200 W, a BCl₃/Cl₂ gas ratio of 3:2. Under this condition, the mesa structure with the etch depth over 1 ㎛ and the etch angle over 75° and also with no etching residue was obtained for the µ-LED chip. The developed ICP showed the improved values on the process pressure, the etch selectivity, the etch depth uniformity, the etch angle profile and the substrate temperature uniformity in comparison with the commercial ICP. The µ-LED chip fabricated using the developed ICP showed the similar or improved characteristics in the L-I-V measurements compared with the one fabricated using the conventional ICP method