• 한국산업보건학회지
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• 제22권1호
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• pp.9-19
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• 2012

Objectives: The aim of this study is to critically review the exposure surrogates and estimates used to associate health effects in wafer fabrication workers such as spontaneous abortion and cancer, as well as to identify the limitations of retrospective exposure assessment methods Methods: Epidemiologic and exposure-assessment studies of wafer fabrication operations in the semiconductor industry were collected. Retrospective exposure-assessment methods used in cancer risk and mortality and reproductive toxicity were reviewed. Results: Eight epidemiologic papers and two reports compared cancer risk among workers in wafer fabrication facilities in the semiconductor industry with the risk of the general population. Exposure surrogates used in those cancer studies were fabrication(vs. non-fabrication), employment duration, manufacturing eras, job title (operator vs. maintenance worker) and qualitative classifications of agents without assessing specific agent or job-specific exposure. In contrast, specific operation, job title and agents were used to classify the exposure of fabrication workers, contributing to finding a significant association with spontaneous abortion (SAB). Conclusion: Further epidemiologic studies of fabrication workers using more refined exposure assessment methods are warranted in order to examine the associations between fabrication work, environment, and specific agents with cancer risk or mortality as used in SAB epidemiologic studies.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.335-336
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• 2006

Compound semiconductor manufacturing environment also has been emerged as mass customization and open foundry service so integrated manufacturing system is needed. In this study, we design data acquisition system of compound semiconductor fabrication that has monitoring and control of process. The developed DAS is consisted of key-in system inputted by operator and automatic acquisition system by GEM protocol. And we implemented them in the actual compound semiconductor. It is expected that using developed system would offer precise process information to buyer, reduce a lead-time, and obey a due-dates and so on.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.72.1-72
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• 1998

• 한국재료학회지
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• 제33권4호
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• pp.142-150
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• 2023

AZO/Cu/AZO thin films were deposited on glass by RF magnetron sputtering. The specimens showed the preferred orientation of (0002) AZO and (111) Cu. The Cu crystal sizes increased from about 3.7 nm to about 8.5 nm with increasing Cu thickness, and from about 6.3 nm to about 9.5 nm with increasing heat treatment temperatures. The sizes of AZO crystals were almost independent of the Cu thickness, and increased slightly with heat treatment temperature. The residual stress of AZO after heat treatment also increased compressively from -4.6 GPa to -5.6 GPa with increasing heat treatment temperature. The increase in crystal size resulted from grain growth, and the increase in stress resulted from the decrease in defects that accompanied grain growth, and the thermal stress during cooling from heat treatment temperature to room temperature. From the PL spectra, the decrease in defects during heat treatment resulted in the increased intensity. The electrical resistivities of the 4 nm Cu film were 5.9×10^-4 Ω·cm and about 1.0×10^-4 Ω·cm for thicker Cu films. The resistivity decreased as the temperature of heat treatment increased. As the Cu thickness increased, an increase in carrier concentration resulted, as the fraction of AZO/Cu/AZO metal film increased. And the increase in carrier concentration with increasing heat treatment temperature might result from the diffusion of Cu ions into AZO. Transmittance decreased with increasing Cu thicknesses, and reached a maximum near the 500 nm wavelength after being heat treated at 200 ℃.

• 한국산업보건학회지
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• 제26권2호
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• pp.188-197
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• 2016

Objectives: The purpose of this study was to evaluate the ozone exposure levels and the variations in ozone concentration in a semiconductor fabrication facility and office in relation to the ozone concentration in the outdoor air. Methods: This study was performed in an office, semiconductor fabrication facility(such as etching, diffusion, diffusion plenum), and outdoors from June to August, 2015. Measurements were taken six times at the same places using an active sampler(pumped) and real-time equipment. Ozone monitoring by the active sampler method and analysis were carried out by OSHA Method ID-214. Real-time measurement was carried out by ozone measuring equipment using a non-dispersive ultraviolet absorption method. Results: Ozone concentrations in the semiconductor fabrication facility and office were 0.7~7.1 ppb in area samples and 0.72~4.07 ppb in real-time measurement, which were 0.88~8.88% of the occupational exposure limit. The concentration of ozone generated by a laser printer in the office was less than 2 ppb. There was not a significant difference between ozone concentrations before and after using the laser printer. The indoor/outdoor concentration ratio(I/O ratio) in the semiconductor fabrication facility and office was 0.05 and 0.06, respectively. Conclusions: All the samples contained ozone levels lower than the occupational exposure limit and it was confirmed that the concentration of outdoor ozone had no significant effect on indoor ozone concentration.

• 한국화재소방학회논문지
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• 제14권4호
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• pp.23-28
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• 2000

반도체 공장의 제연설계를 위한 성능기준 설계를 분석하였다. 사례분석을 통하여 제연 설계 시스템의 성능평가 기준을 설정하고 최적의 배연 방법을 분석하기 위한 FDS 화재모델링을 수행하였다. 제연 설계 지침이나 관련 법규 또는 표준화된 기준이 부족한 한국과 미국의 현실에서 본 연구의 성능기준 설계 방법은 반도체공장의 제연 설계를 위한 현실적인 적용과 활용이 기대된다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.99.3-99
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• 1998

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• 산업공학
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• 제12권3호
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.