• 산업경영시스템학회지
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• 제45권4호
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• pp.86-98
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• 2022

Recently, many studies have been conducted to improve quality by applying machine learning models to semiconductor manufacturing process data. However, in the semiconductor manufacturing process, the ratio of good products is much higher than that of defective products, so the problem of data imbalance is serious in terms of machine learning. In addition, since the number of features of data used in machine learning is very large, it is very important to perform machine learning by extracting only important features from among them to increase accuracy and utilization. This study proposes an anomaly detection methodology that can learn excellently despite data imbalance and high-dimensional characteristics of semiconductor process data. The anomaly detection methodology applies the LIME algorithm after applying the SMOTE method and the RFECV method. The proposed methodology analyzes the classification result of the anomaly classification model, detects the cause of the anomaly, and derives a semiconductor process requiring action. The proposed methodology confirmed applicability and feasibility through application of cases.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.280-287
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• 2002

We present technical issues involved in the development of actuators and sensors for applications to high-precision Micro Electro Mechanical System (MEMS). The technical issues include fabrication uncertainty and noise disturbance, causing major difficulties for MEMS to achieve high-precision actuation and detection functions. For nano-precision actuators, we solve the fabrication instability and electrical noise problems using digital actuators coupled with nonlinear mechanical modulators. For the high-precision capacitive sensors, we present a branched finger electrodes using high-amplitude anti-phase sensing signals. We also demonstrate the potential applications of the nanoactuators and nanodetectors to high-precision positioning MEMS.

• 한국표면공학회지
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• 제48권6호
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• pp.360-370
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• 2015

As the size of the semiconductor devices shrinks to nanometer scale, the importance of plasma etching process to the fabrication of nanometer scale semiconductor devices is increasing further and further. But for the nanoscale devices, conventional plasma etching technique is extremely difficult to meet the requirement of the device fabrication, therefore, other etching techniques such as use of multi frequency plasma, source/bias/gas pulsing, etc. are investigated to meet the etching target. Until today, various pulsing techniques including pulsed plasma source and/or pulse-biased plasma etching have been tested on various materials. In this review, the experimental/theoretical studies of pulsed plasmas during the nanoscale plasma etching on etch profile, etch selectivity, uniformity, etc. have been summarized. Especially, the researches of pulsed plasma on the etching of silicon, $SiO_2$, and magnetic materials in the semiconductor industry for further device scaling have been discussed. Those results demonstrated the importance of pulse plasma on the pattern control for achieving the best performance. Although some of the pulsing mechanism is not well established, it is believed that this review will give a certain understanding on the pulsed plasma techniques.

• 한국가스학회지
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• 제22권1호
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• pp.78-85
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• 2018

본 연구를 통하여 반도체 FPD 제조설비 및 클린룸에 관련한 설비의 위험성분석과 그에 대한 근원적인 안전대책을 연구하고, 설비 및 환경의 특수성을 고려한 방폭 설계 모델링화를 검토하여 관련 설비의 설계 및 제작에 기술적인 기준과 근거로 활용하고자 하며, 아래와 같은 성과로서 향후 반도체 FPD 산업의 기술적 기준 수립 및 관련 산업에 기여할 것으로 생각한다. 1) 관련 국제 기술규격과 법령, 설비의 특성을 반영한 FAB 장비의 최적화된 폭발위험장소의 모델링 도출 2) FAB 장비 및 클린 룸의 특성을 고려한 위험설비의 안전성 확보 (Fool-Proof와 Fail Safe)를 위한 안전시스템 구축방안과 안전기준 및 대책 도출 3) 향후 FAB 장비의 방폭 설계에 대한 가장 효율적인 기준 적용을 통한 신규 FAB 장비의 방폭 성능의 유연성 확보하고 수립된 안전기준을 통한 설비와 안전시스템의 신뢰성 검증 절차 운영을 위한 "안전인증제도"의 자율적 향상화.

• 지능정보연구
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• 제9권1호
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• pp.157-177
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• 2003

본 논문은 반도체 FAB공정의 수율개선 및 예측을 위해 데이터마이닝 기법을 적용한 사례를 소개한다. FAB 공정의 복잡성과 생산현장에서 수집되는 방대한 기술데이터로 인해 기존의 통계적 방법이나 엔지니어의 경험적 분석 방법만으로는 미처 파악하지 못하는 수율 저하 요인이 상당 수 존재한다. 본 논문은 먼저, FAB공정을 마친 웨이퍼에 불량 칩(chip)이 지리적으로 특정 위치에 집중적으로 발생하는 현상을 육안검사 대신 군집분석을 이용하여 데이터로부터 자동 판별할 수 있는 방법을 제안한다. 다음으로 연속패턴분석, 분류분석, RBF(Radial Base Function) 기법을 적용하여 수율 저하의 원인이 되는 문제 장비나 문제 파라미터를 신속, 정확하게 파악할 수 있도록 해 줄 뿐만 아니라 공정 진행 중인 제품의 미래 수율을 예측할 수 있도록 지원하는 방법을 제안한다. 또한 위 기법들을 반도체 FAB공정을 대상으로 국내 모 반도체 회사에서 정보시스템으로 구현한 Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis ＆ Up Support) 시스템을 소개한다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

• 경영과학
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• 제32권4호
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• pp.69-80
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• 2015

The semiconductor industry is one of those in which the most intricate processes are involved and there are many critical factors that are controlled with precision in those processes. Naturally production scheduling in the semiconductor industry is also very complex and studied by the industry and academia for many years; however, still there are many issues left unclear in the problem. This paper proposes an multi-objective optimization-based scheduling method for semiconductor fabrication(fab). Two main objectives are throughput maximization and meeting target production quantities. The first objective aims to reduce production cost, especially the fixed cost incurred by a large investment constructing a new fab facility. The other is meeting customer orders on time and also helps a fab maintain stable throughput through controlled WIP balancing in the long run. The paper shows a trade-off structure between the two objectives through experimental studies, which provides industrial practitioners with useful references.

• 분석과학
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• 제5권4호
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• pp.359-366
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• 1992

본 논문은 마이크로 Raman 분광분석법을 이용하여 국부적 열산화 후 실리콘 표면에 유입되는 스트레스를 평가한 것이다. 국부적 열산화 후 실리콘 표면에 유입되는 스트레스는 실리콘 산화막과 active 영역의 경계 부분에서 최대치를 나타내었다. Active 영역의 크기가 작아질수록 스트레스량은 증가하며, 이는 스트레스가 active 영역의 크기에 의존함을 보여 주는 것이다. 또한, active 영역이 $0.45{\mu}m$인 세 가지 소자 분리 공정, A, B, moB를 평가한 결과 moB 공정의 스트레스 값이 가장 작았으며, 새부리 효과도 가장 작았다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.454-461
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• 2015

Light enhancement of GaN based light emitting diodes (LEDs) have been investigated by texturing the top p-GaN surface. Nano-textured LEDs have been fabricated using self-assembled Ni nano mask during dry etching process. Experimental results were further compared with simulation data. Three types of LEDs were fabricated: Conventional (planar LED), Surface nano-porous (porous LED) and Surface nano-cluster (cluster LED). Compared to planar LED there were about 100% and 54% enhancement of light output power for porous and cluster LED respectively at an injection current of 20 mA. Moreover, simulation result showed consistency with experimental result. The increased probability of light scattering at the nano-textured GaN-air interface is the major reason for increasing the light extraction efficiency.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.