• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.46-56
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• 2020

This article highlights new opportunities of inorganic semiconductor materials for bio-implantable electronics, as a subset of 'transient' technology defined by an ability to physically dissolve, chemically degrade, or disintegrate in a controlled manner. Concepts of foundational materials for this area of technology with historical background start with the dissolution chemistry and reaction kinetics associated with hydrolysis of nanoscale silicon surface as a function of temperature and pH level. The following section covers biocompatibility of silicon, including related other semiconductor materials. Recent transient demonstrations of components and device levels for bioresorbable implantation enable the future direction of the transient electronics, as temporary implanters and other medical devices that provide important diagnosis and precisely personalized therapies. A final section outlines recent bioresorbable applications for sensing various biophysical parameters, monitoring electrophysiological activities, and delivering therapeutic signals in a programmed manner.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.603-605
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• 1995

We present a novel method. to fabricate surface micromachined structures without their sticking on the substrate. An anhydrous HF/$CH_3OH$ vapor-phase etching (VPE) of sacrificial $SiO_2$ layers was employed to release 0.5-2 {\mu}m$ thick polysilicon cantilevers. The fabricated structures were observed using scanning electron microscope and 3-dimensional optical microscope. The results show that we can successfully make cantilever beams up to 1200{\mu}m$ long without sticking. Annealing effects on residual stress of polysilicon microstructures were also investigated. Anneal ins at 1100$^{\circ}C$ for 1 hour was found to be effective to release the residual stress of the polysilicon microstructures. These VPE and anneal ins techniques will be useful in surface micromachining technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.221-228
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• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.187-187
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• 2007

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence (< $200^{\circ}C$) on electrical properties. The feasible application in 1~2GHz frequency from measured data $BV_{CEO}$ ~10V, $f_r$~14 GHz, ${\beta\simeq}110$, NF~1 dB using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.2
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.1
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• pp.119-126
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• 1993

We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.

• Journal of the Korea Safety Management & Science
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• v.6 no.4
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• pp.155-170
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• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• Journal of Sensor Science and Technology
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• v.28 no.1
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• pp.23-29
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• 2019

A copper tetracumylphenoxy phthalocyanine (CuPccp) thin film was formed on an organic insulator film by Langmuir-Blodgett (LB) deposition for gas sensor fabrication. To increase the reproducibility of film transfer, stearyl alcohol was used as a transfer promoter. The structural properties of the CuPccp layers were optically monitored through attenuated total reflection and polarization-modulated ellipsometry techniques. The average thickness of a single layer of the CuPccp LB film was measured to be 2.5 nm. Despite the role of the transfer promoter, the stability of the layer transfer was not sufficient to ensure homogeneity of the LB film. This was probably due to the presence of aggregates in the molecular structure of the CuPccp LB film. Nevertheless, copper phthalocyanine polymorphism can be greatly suppressed by the LB arrangement, which appears to contribute to the improvement of electrical conductivity. The p-type semiconductor characteristics were confirmed by Hall measurements from the CuPccp LB films.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• Journal of Environmental Science International
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• v.9 no.4
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• pp.325-330
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• 2000

The hydroxyapatite (HAp) for the present study was prepared by precipitation method in semiconductor fabrication and the crystallized at ambient to 95$0^{\circ}C$ for 30min in electric furnace. The ion-exchange characteristics of HAp for various heavy metal ions such as $Cd^{2+}, Cu^{2+}, Mn^{2+}, Zn^{2+}, Fe^{2+}, Pb^{2+}, Al^{3+}, and Cr^{6+}$ in aqueous solution has been investigated. The removal ratio of various metal ions for HAp were investigated with regard to reaction time, concentration of standard solution, amount of HAp and pH of solution. The order of the ions exchanged amount was as follws: $Pb^{2+}, Fe^{3+}>Cu^{2+}>Zn^{2+}>Al^{3+}>Cd^{2+}>Mn^{2+}>Cr^{6+}. The Pb^{2+}$ ion was readily removed by the Hap, even in the strongly acidic region. The maximum amount of the ion-exchange equilibrium for $Pb^{2+}$ ion was about 45 mg/gram of HAp. The HAp would seem to be possible agent for the removal of heavy metal ions in waste water by recycling of waste sludge in semiconductor fabrication.