• 산업공학
• /
• 제21권2호
• /
• pp.141-150
• /
• 2008

In this paper, an efficient control method for semiconductor fabrication process is presented. Generally, control is performed with data which is under the influence of process disturbance. EWMA is one of the most popular control methods in semiconductor fabrication that effectively deals with varying process condition. A new method using EWMA, called the Dual Damping EWMA, is presented in this study to reduce over-control by separating weight factor of input and output. The goal is to reflect Drift but reduce the effects of White noise in run to run control. Simulation is performed to evaluate the performance of DPEWMA and to compare with EWMA and Double EWMA.

• Current Photovoltaic Research
• /
• 제4권3호
• /
• pp.108-113
• /
• 2016

III-V compound semiconductor based thin film solar cells promise relatively higher power conversion efficiencies and better device reliability. In general, the thin film III-V solar cells are fabricated by an epitaxial lift-off process, which requires an $Al_xGa_{1-x}As$ ($x{\geq}0.8$) sacrificial layer and an inverted solar cell structure. However, the device performance of the inversely grown solar cell could be degraded due to the different internal diffusion conditions. In this study, InGaP/GaAs double-junction solar cells are inversely grown by MOCVD on GaAs (100) substrates. The thickness of the GaAs base layer is reduced to minimize the thermal budget during the growth. A wide band gap p-AlGaAs/n-InGaP tunnel junction structure is employed to connect the two subcells with minimal electrical loss. The solar cell structures are transferred on to thin metal films formed by Au electroplating. An AlAs layer with a thickness of 20 nm is used as a sacrificial layer, which is removed by a HF:Acetone (1:1) solution during the epitaxial lift-off process. As a result, the flexible InGaP/GaAs solar cell was fabricated successfully with an efficiency of 27.79% under AM1.5G illumination. The efficiency was kept at almost the same value after bending tests of 1,000 cycles with a radius of curvature of 10 mm.

• 산업경영시스템학회지
• /
• 제45권3호
• /
• pp.40-48
• /
• 2022

An automated material handling system (AMHS) has been emerging as an important factor in the semiconductor wafer manufacturing industry. In general, an automated guided vehicle (AGV) in the Fab's AMHS travels hundreds of miles on guided paths to transport a lot through hundreds of operations. The AMHS aims to transfer wafers while ensuring a short delivery time and high operational reliability. Many linear and analytic approaches have evaluated and improved the performance of the AMHS under a deterministic environment. However, the analytic approaches cannot consider a non-linear, non-convex, and black-box performance measurement of the AMHS owing to the AMHS's complexity and uncertainty. Unexpected vehicle congestion increases the delivery time and deteriorates the Fab's production efficiency. In this study, we propose a Q-Learning based dynamic routing algorithm considering vehicle congestion to reduce the delivery time. The proposed algorithm captures time-variant vehicle traffic and decreases vehicle congestion. Through simulation experiments, we confirm that the proposed algorithm finds an efficient path for the vehicles compared to benchmark algorithms with a reduced mean and decreased standard deviation of the delivery time in the Fab's AMHS.

• Transactions on Electrical and Electronic Materials
• /
• 제14권5호
• /
• pp.254-257
• /
• 2013

In-situ optical emission spectroscopy (OES) is employed for PECVD chamber monitoring. OES is used as an addon sensor to monitoring and cleaning end point detection (EPD). On monitoring plasma chemistry using OES, the process gas and by-product gas are simultaneously monitored. Principal component analysis (PCA) enhances the capability of end point detection using OES data. Through chamber cleaning monitoring using OES, cleaning time is reduced by 53%, in general. Therefore, the gas usage of fluorine is also reduced, so satisfying Green Fab challenge in semiconductor manufacturing.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권5호
• /
• pp.533-538
• /
• 2015

Thermal characterization of individual pixels in microbolometer infrared image sensors is needed for optimal design and improved performance. In this work, we used thermoreflectance microscopy on uncooled microbolometer image sensors to investigate the thermal characteristics of individual pixels. Two types of microbolometer image sensors with a shared-anchor structure were fabricated and thermally characterized at various biases and vacuum levels by measuring the temperature distribution on the surface of the microbolometers. The results show that thermoreflectance microscopy can be a useful thermal characterization tool for microbolometer image sensors.

• 대한산업공학회지
• /
• 제41권3호
• /
• pp.267-274
• /
• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• 산업경영시스템학회지
• /
• 제37권4호
• /
• pp.126-133
• /
• 2014

This paper addresses order-lot pegging issues in the supply chain of a semiconductor business. In such a semiconductor business (memory or system LSI) order-lot pegging issues are critical to achieving the goal of ATP (Available to Promise) and on-time production and delivery. However existing pegging system and researches do not consider capacity limit on bottleneck steps. This paper presents an order-lot pegging algorithm for assigning a lot to an order considering quality constraints of each lot and capacity of bottleneck steps along the entire FAB. As a result, a quick and accurate response can be provided to customer order enquiries and pegged lot lists for each promised orders can be shown transparently and short or late orders can be detected before fixing the order.

• 반도체디스플레이기술학회지
• /
• 제7권2호
• /
• pp.39-43
• /
• 2008

Productivity is one of the performance indices of the semiconductor equipment in manufacturing viewpoint. Among many ways tried and adopted for improvement of the productivity of the FAB equipment, variation of equipment configuration was considered and its effect on the throughput was analyzed. Parallel machine cycle charts that were generated based on the equipment log were used in the analysis. Efficiency of the equipment due to change of the structure and the probability of the usage in the manufacturing process were examined. The results showed that the modification of the control algorithm in the equipment and the redistribution of the process time for each process and transfer module along to the change in the structure enhance the throughput of the equipment.

• 산업공학
• /
• 제10권1호
• /
• pp.1-13
• /
• 1997

반도체 Wafer Fabrication 공정은 무수한 공정과 복잡한 Lot의 흐름 등으로 다른 제조 형태에 비해 효율적인 관리가 대단히 어려운 부문이다. 본 연구는 반도체 Fab을 대상으로 주어진 생산 소요량과 목표 공기를 효율적으로 달성하기 위한 Shift 단위의 생산 일정계획을 대상으로 하였다. 특히, 전 공정 및 장비를 고려하기보다는 Bottleneck인 Photo 공정의 Stepper를 중심으로, 공정을 Layer단위로 묶어, 한 Shift에서 어떻게 Stepper를 할당하고 생산계획을 할 것인가를 결정하기 위한 2단계 방법론을 제시하고, Stepper 할당 및 계획에 필요한 3가지 알고리즘들을 제시하였다. 이 기법들을 소규모의 예제들에 대해 적용한 결과와 최적해와의 비교를 통하여 그 성능을 평가하였다.

• 한국시뮬레이션학회:학술대회논문집
• /
• 한국시뮬레이션학회 2001년도 The Seoul International Simulation Conference
• /
• pp.269-273
• /
• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.