• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.214-223
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• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• Journal of Korean Institute of Industrial Engineers
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• v.33 no.2
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• pp.166-173
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• 2007

In this paper, we propose a model-based approach to estimating production parameters of semiconductor FAB equipment. For FAB scheduling, for example, we need to know equipment's production parameters such as flow time, tact time, setup time, and down time. However, these data are not available, and they have to be estimated from material move data such as loading times and unloading times that are automatically collected in modern automated semiconductor FAB. The proposed estimation method may be regarded as a Bayes estimation method because we use additional information about the production parameters. Namely, it is assumed that the technical ranges of production parameters are known. The proposed estimation method has been applied to a LCD FAB, and found to be valid and useful.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.385-386
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• 2008

Reducing the PR(Photoresist) dispense Rate is one of the important issues in Photolithography. It is a main concern that variation in PR dispense rate and existance of microbubble. so we need to measure the photoresist dispense rate more precisely. This paper presented a noble sensor of measuring the PR dispense and detecting the microbubble.

• IE interfaces
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• v.17 no.spc
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• pp.131-140
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• 2004

The purpose of this paper is to develop and show the efficiency of the URL(Unload Request Logic) and LRL(Load Request Logic) of the dispatcher in the Fab(Fabrication) Manufacturing Execution System. These logics are the core procedures which control the material(wafer and glass substrate) flow efficiently in the semiconductor and LCD fab considering inter-bay as well as intra-bay material flow. We use the present and future status information of the system by look-ahead and the information about the future transportation schedule of Automated Guided Vehicles. The simulation results show that the URL and LRL presented in this paper reduce the average lead time, average and maximum WIP level, and the average available AGV waiting time.

• Korean Management Science Review
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• v.32 no.4
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• pp.69-80
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• 2015

The semiconductor industry is one of those in which the most intricate processes are involved and there are many critical factors that are controlled with precision in those processes. Naturally production scheduling in the semiconductor industry is also very complex and studied by the industry and academia for many years; however, still there are many issues left unclear in the problem. This paper proposes an multi-objective optimization-based scheduling method for semiconductor fabrication(fab). Two main objectives are throughput maximization and meeting target production quantities. The first objective aims to reduce production cost, especially the fixed cost incurred by a large investment constructing a new fab facility. The other is meeting customer orders on time and also helps a fab maintain stable throughput through controlled WIP balancing in the long run. The paper shows a trade-off structure between the two objectives through experimental studies, which provides industrial practitioners with useful references.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.51-55
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• 2004

In the design stage of high precision manufacturing/inspection FAB facilities, it is necessary to investigate the allowable vibration limits of high precision equipments and to study structural dynamic characteristics of C/R and Sub-structure in order to provide structural vibration criteria to satisfy these allowable limits. The goal of this study is to investigate the dynamic characteristics of PC-Type mock-up structures designed for next generation TFT-LCD FAB through experiments and analysis procedures. Therefore, in order to provide a proper dynamic structural design for high precision manufacturing/inspection work process, these allowable limits must be satisfied.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.91-97
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• 2009

The performance of GaInP/GaAs tandem solar cells with AlInP growth temperatures of 680$^{\circ}C$ and 700 $^{\circ}C$ on n-type GaAs (100) substrate with 2$^{\circ}$ and 6$^{\circ}$ tilt angles has been investigated. The series resistance and open circuit voltage of the fabricated tandem solar cells are affected by the substrate tilt angles and the growth temperatures of the window layer when zinc is doped in the tunnel diode. With carbon doping as a p-type doping source in the tunnel diode and the effort of current matching between top and bottom cells, GaInP/GaAs tandem solar cell has been exhibited 25.58% efficiency.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.11a
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• pp.115-121
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• 2002

The growth of semiconductor industry attracted to researchers like design, facility technique and making small size chip areas. But nowadays, cause of technology extension and oversupply and price down, yield improvement is the most important point on growth. This paper describes the computer mode]ing technique as the solutions to analyze the problem, to formalize the semiconductor manufacturing process and to build advanced manufacturing environments. The computer models are built referring an existing 8' wafer production line in Korea.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.25 no.2
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• pp.202-210
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• 2015

Objectives: The purpose of this study was to examine clean room(C/R) structure, air conditioning and contamination control systems and to provide basic information for identifying a correlation between the semiconductor work environment and workers' disease. Methods: This study was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. The C/R structure and air conditioning method were investigated using basic engineering data from documentation for C/R construction. Furthermore, contamination parameters such as airborne particles, temperature, humidity, acids, ammonia, organic compounds, and vibration in the C/R were based on the International Technology Roadmap for Semiconductors(ITRS). The properties of contamination control systems and the current status of monitoring of various contaminants in the C/R were investigated. Results: 200 mm and 300 mm wafer fabrication facilities were divided into fab(C/R) and sub fab(Plenum), and fab, clean sub fab and facility sub fab, respectively. Fresh air(FA) is supplied in the plenum or clean sub fab by the outdoor air handling unit system which purifies outdoor air. FA supply or contaminated indoor air ventilation rates in the 200 mm and 300 mm wafer fabrication facilities are approximately 10-25%. Furthermore, semiconductor clean rooms strictly controlled airborne particles(${\leq}1,000{\sharp}/ft^3$), temperature($23{\pm}0.5^{\circ}C$), humidity($45{\pm}5%$), air velocity(0.4 m/s), air change(60-80 cycles/hr), vibration(${\leq}1cm/s^2$), and differential pressure(atmospheric pressure$+1.0-2.5mmH_2O$) through air handling and contamination control systems. In addition, acids, alkali and ozone are managed at less than internal criteria by chemical filters. Conclusions: Semiconductor clean rooms can be a pleasant environment for workers as well as semiconductor devices. However, based on the precautionary principle, it may be necessary to continuously improve semiconductor processes and the work environment.