• 한국재료학회지
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• 제34권2호
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• pp.105-110
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• 2024

Scanning probe microscopy (SPM) has become an indispensable tool in efforts to develop the next generation of nanoelectronic devices, given its achievable nanometer spatial resolution and highly versatile ability to measure a variety of properties. Recently a new scanning probe microscope was developed to overcome the tip degradation problem of the classic SPM. The main advantage of this new method, called Reverse tip sample (RTS) SPM, is that a single tip can be replaced by a chip containing hundreds to thousands of tips. Generally for use in RTS SPM, pyramid-shaped diamond tips are made by molding on a silicon substrate. Combining RTS SPM with Scanning spreading resistance microscopy (SSRM) using the diamond tip offers the potential to perform 3D profiling of semiconductor materials. However, damage frequently occurs to the completed tips because of the complex manufacturing process. In this work, we design, fabricate, and evaluate an RTS tip chip prototype to simplify the complex manufacturing process, prevent tip damage, and shorten manufacturing time.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.237.1-237.1
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• 2014

Etching is one of the most important steps in semiconductor manufacturing. In etch process control a critical task is to stop the etch process when the layer to be etched has been removed. If the etch process is allowed to continue beyond this time, the material gets over-etched and the lower layer is partially removed. On the other hand if the etch process is stopped too early, part of the layer to be etched still remains, called under-etched. Endpoint detection (EPD) is used to detect the most accurate time to stop the etch process in order to avoid over or under etch. The goal of this research is to develop a hardware and software system for EPD. The hardware consists of an Optical Plasma Monitor (OPM) sensor which is used to continuously monitor the plasma optical emission intensity during the etch process. The OPM software was developed to acquire and analyze the data to perform EPD. Our EPD algorithm is based on the following theory. As the etch process starts the plasma generated in the vacuum is added with the by-products from the etch reactions on the layer being etched. As the endpoint reaches and the layer gets completely removed the plasma constituents change gradually changing the optical intensity of the plasma. Although the change in optical intensity is not apparent, the difference in the plasma constituents when the endpoint has reached leaves a unique signature in the data gathered. Though not detectable in time domain, this signature could be obscured in the frequency spectrum of the data. By filtering and analysis of the changes in the frequency spectrum before and after the endpoint we could extract this signature. In order to do that, first, the EPD algorithm converts the time series signal into frequency domain. Next the noise in the frequency spectrum is removed to look for the useful frequency constituents of the data. Once these useful frequencies have been selected, they are monitored continuously in time and using a sub-algorithm the endpoint is detected when significant changes are observed in those signals. The experiment consisted of three kinds of etch processes; ashing, SiO2 on Si etch and metal on Si etch to develop and evaluate the EPD system.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.440-440
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• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.93-101
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• 2002

We have proposed and fabricated two lateral type field emission diodes, poly-Si emitter by utilizing the local oxidation of silicon (LOCOS) and GaN emitter using metal organic chemical vapor deposition (MOCVD) process. The fabricated poly-Si diode exhibited excellent electrical characteristics such as a very low turn-on voltage of 2 V and a high emission current of $300{\;}\bu\textrm{A}/tip$ at the anode-to-cathode voltage of 25 V. These superior field emission characteristics was speculated as a result of strong surface modification inducing a quasi-negative electron affinity and the increase of emitting sites due to local sharp protrusions by an appropriate activation treatment. In respect, two kinds of procedures were proposed for the fabrication of the lateral type GaN emitter: a selective etching method with electron cyclotron resonance-reactive ion etching (ECR-RIE) or a simple selective growth by utilizing $Si_3N_4$ film as a masking layer. The fabricated device using the ECR-RIE exhibited electrical characteristics such as a turn-on voltage of 35 V for $7\bu\textrm{m}$ gap and an emission current of~580 nA/l0tips at anode-to-cathode voltage of 100 V. These new field emission characteristics of GaN tips are believed to be due to a low electron affinity as well as the shorter inter-electrode distance. Compared to lateral type GaN field emission diode using ECR-RIE, re-grown GaN emitters shows sharper shape tips and shorter inter-electrode distance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.263-267
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• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• 대한전자공학회논문지SD
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• 제47권4호
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• pp.20-25
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• 2010

평판형 rib 도파로의 설계 및 공정기술을 바탕으로 632.8 nm에서 동작하는 집적 마흐젠더 간섭계 센서(Mach-Zehnder interferometric sensor)를 제작하였다. 단일모드와 높은 감도의 두 가지 조건을 고려하여 실리카 계열($SiO_2-SiO_xN_y-SiO_2$) rib 도파로를 설계하였고 박막증착, 사진제판, RIE (Reactive Ion Etching)와 같은 반도체 공정들을 이용해 그 기하학적 구조를 구현하였다. 제작된 rib 도파로의 광출력을 cut-back방법으로 분석한 결과, 약 4.82 dB/cm의 전파손실을 측정하였다. 동시에 크롬 식각방지 층 공정을 도입하여 마흐젠더 간섭계 칩 위에 감지영역(sensing zone)을 형상화할 때 발생하는 코어 층 손상을 방지하였다. 제작된 마흐젠더 간섭계 센서를 이용한 증류수/에탄올 혼합물 굴절률 측정실험을 통해 약 $\pi$/($4.04{\times}10^{-3}$)의 소자 감도(sensitivity)를 최종 확인하였다.

• 한국광학회:학술대회논문집
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• 한국광학회 2000년도 하계학술발표회
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• pp.28-29
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• 2000

Optical power splitters and/or couplers are important components for optical signal distribution between channels both in wavelength division multiplexing(WDM) systems and photonic integrated circuits(PICs). Since polarization is usually not known after propagation in an optical fiber, passive WDM components have to be polarization insensitivity, Compared to alternatives such as directional couplers or Y-junction splitters, splitters based on multimode interference(MMI) have found a growing interest in recent yens because of their desirable characteristics, such as compact size, low excess loss, wide bandwidth, polarization independence, and relaxed fabrication tolerances$^{(1)}$ . These devices have been fabricated in polymers, silica, or III-V semiconductor materials. A1 $\times$ 4 MMI power splitter on InP materials that were suitable for application in the 1.55-${\mu}{\textrm}{m}$ region$^{(2)}$ . However, the fabrication process of the structure is too complicated and the photolithography tolerance is very tight. Also, a 1 $\times$ 16 InGaAsP/InP MMI power splitter with an excess loss of 2.2dB and a splitting ratio of 1.5dB was demonstrated by using deep etching$^{(3)}$ . The deep etching of the sidewalls through the entire guide layer of the slab waveguide resulted in a number of drawbacks$^{(4)}$ . (omitted)

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• 한국산업융합학회 논문집
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• 제10권4호
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• pp.213-219
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• 2007

Glass-to-metal contact should be prevented in the design of any structural glass component. Because glass is extremely brittle and will fracture readily if even a small point load is applied. If the assembly includes a glass component supported by metallic structure, designers should provide a pliable interface of some kind between the two parts. But there happens high demand of glass-to metal contact in semiconductor industries due to adoption of dry cleaning process as one of the good solution to reduce running cost - carry out equipments cleaning with high corrosive and etching gas such as CF4 with keeping process temperature as the same as high service temperature. Therefore the quartz glass have to be received compression by direct contact with metal as the form of weight itself and vacuum pressure and fatigue by vibrations caused by process during the process. In this paper investigation will be carried out on fracture behavior of quartz glass contacted with metal directly under local load and fatigue given by process vibration with apparatus which can give $lox{\backslash}cal$ load and vibration through PZT ceramics to give guideline to prevent unintended fracture of quartz glass.