• 전기전자학회논문지
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• 제19권1호
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• pp.41-44
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• 2015

소자의 집적화에 필수적인 소자 분리공정에서 화학약품의 오염 문제등을 발생시키는 화학적 기계연마기술(CMP) 공정을 사용하지 않고 벌크 finFET(fin field effect transistor) 의 트랜치 구조를 형성할 수 있는 공정에 대하여 제안하였다. 사진 감광막 도포시 발생하는 두께차이와 희생층으로 사용되는 실리콘 질화막을 사용하면 에칭 공정만을 사용하여 상대적으로 표면 위로 돌출된 부분의 실리콘 산화막 층을 에칭하는 것은 물론 finFET 의 채널로 사용되는 실리콘 트랜치 구조를 한번에 형성할 수 있는 특징을 갖는다. 본 연구에서는 AZ1512 사진 감광막을 사용하여 50 나노미터급 실리콘 트랜치 구조를 형성하는 공정을 수행하였으며 그 결과를 소개한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.233-233
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• 2010

Magnetic random access memory (MRAM), based on magnetic tunnel junction (MTJ) and CMOS, is a prominent candidate among prospective semiconductor memories because it can provide nonvolatility, fast access time, unlimited read/write endurance, low operating voltage and high storage density. The etching of MTJ stack with good properties is one of a key process for the realization of high density MRAM. In order to achieve high quality MTJ stack, the use of CoFeB and IrMn magnetic films as free layers was proposed. In this study, inductively coupled plasma reactive ion etching of CoFeB and IrMn thin films masked with Ti hard mask was investigated in a $Cl_2$/Ar gas mix. The etch rate of CoFeB and IrMn films were examined on varying $Cl_2$ gas concentration. As the $Cl_2$ gas increased, the etch rate monotonously decreased. The effective of etch parameters including coil rf power, dc-bais voltage, and gas pressure on the etch profile of CoFeB and IrMn thin film was explored, At high coil rf power, high dc-bais voltage, low gas pressure, the etching of CoFeB and IrMn displayed better etch profiles. Finally, the clean and vertical etch sidewall of CoFeB and IrMn free layers can be achieved by means of thin Ti hard mask in a $Cl_2$/Ar plasma at the optimized condition.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.213-213
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• 2010

Magnetic random access memory (MRAM), based on magnetic tunnel junction (MTJ) and CMOS, is one of the best semiconductor memories because it can provide nonvolatility, fast access time, unlimited read/write endurance, low operating voltage and high storage density. For the realization of high density MRAM, the etching of MTJ stack with good properties is one of a key process. Recently, there has been great interest in the MTJ stack using MgO as barrier layer for its huge room temperature MR ratio. The use of MgO barrier layer will undoubtedly accelerate the development of MTJ stack for MRAM. In this study, high-density plasma reactive ion etching of MgO films was investigated in an inductively coupled plasma of $Cl_2$/Ar gas mixes. The etch rate, etch selectivity and etch profile of this magnetic film were examined on vary gas concentration. As the $Cl_2$ gas concentration increased, the etch rate of MgO monotonously decreased and etch slop was slanted. The effective of etch parameters including coil rf power, dc-bais voltage, and gas pressure on the etch profile of MgO thin film was explored, At high coil rf power, high dc-bais voltage, low gas pressure, the etching of MgO displayed better etch profiles. Finally, the clean and vertical etch sidewall of MgO films was achieved using $Cl_2$/Ar plasma at the optimized etch conditions.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.345-346
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• 2013

InGaN material is being studied increasingly as a prospective material for solar cells. One of the merits for solar cell applications is that the band gap energy can be engineered from 0.7 eV for InN to 3.4 eV for GaN by varying of indium composition, which covers almost of solar spectrum from UV to IR. It is essential for better cell efficiency to improve not only the crystalline quality of the epitaxial layers but also fabrication of the solar cells. Fabrication includes transparent top electrodes and surface texturing which will improve the carrier extraction. Surface texturing is one of the most employed methods to enhance the extraction efficiency in LED fabrication and can be formed on a p-GaN surface, on an N-face of GaN, and even on an indium tin oxide (ITO) layer. Surface texturing method has also been adopted in InGaN-based solar cells and proved to enhance the efficiency. Since the texturing by direct etching of p-GaN, however, was known to induce the damage and result in degraded electrical properties, texturing has been studied widely on ITO layers. However, it is important to optimize the ITO thickness in Solar Cells applications since the reflectance is fluctuated by ITO thickness variation resulting in reduced light extraction at target wavelength. ITO texturing made by wet etching or dry etching was also revealed to increased series resistance in ITO film. In this work, we report a new way of texturing by deposition of thickness-optimized ITO films on ITO nano dots, which can further reduce the reflectance as well as electrical degradation originated from the ITO etching process.

• 반도체디스플레이기술학회지
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• 제21권1호
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• pp.95-102
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• 2022

Since the organic light-emitting diodes (OLEDs) have been widely investigated as next-generation displays, it has been successfully commercialized as a flexible and rollable display. However, there is still wide room and demand to improve the device characteristics such as power efficiency and lifetime. To solve this issue, there has been a wide research effort, and among them, the internal and the external light extraction techniques have been attracted in this research field by its fascinating characteristic of material independence. In this study, a micro-nano composite structured external light extraction layer was demonstrated. A reactive ion etching (RIE) process was performed on the surfaces of hexagonally packed hemisphere micro-lens array (MLA) and randomly distributed sphere diffusing films to form micro-nano composite structures. Random nanostructures of different sizes were fabricated by controlling the processing time of the O₂ / CHF₃ plasma. The fabricated device using a micro-nano composite external light extraction layer showed 1.38X improved external quantum efficiency compared to the reference device. The results prove that the external light extraction efficiency is improved by applying the micro-nano composite structure on conventional MLA fabricated through a simple process.

• 한국진공학회지
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• 제20권5호
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• pp.322-326
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• 2011

상부 전극에 RF power 가 직접 인가되는 capacitively coupled plasma source를 이용한 oxide layer etching 공정은 현재 반도체 제조 공정에서 매우 유용하게 사용되고 있는 방식이다. 그러나 디바이스의 사이즈가 점점 작아지면서 공정을 진행하기 위한 RF power도 커지고, plasma ignition 되는 electrode 사이의 간격도 점점 좁아지는 기술적 변화가 이루어지고 있다. 이러한 H/W의 변화에 따라 예상치 못한 문제들로 공정을 적용하는데 많은 문제점이 발생하고 있는데, 공정 진행 시에 plasma의 영향으로 인한 electrode의 온도 변화도 그 중 하나이다. 이러한 온도 변화로 인해 wafer to wafer의 공정 진행 결과가 서로 다르게 나타나게 하는 문제가 야기되고 있다. 아래의 내용에서는 상부 electrode의 온도 변화에 따른 etch 특성을 연구하고, 이를 개선할 수 있는 방법에 대해 논하고자 한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.454-461
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• 2015

Light enhancement of GaN based light emitting diodes (LEDs) have been investigated by texturing the top p-GaN surface. Nano-textured LEDs have been fabricated using self-assembled Ni nano mask during dry etching process. Experimental results were further compared with simulation data. Three types of LEDs were fabricated: Conventional (planar LED), Surface nano-porous (porous LED) and Surface nano-cluster (cluster LED). Compared to planar LED there were about 100% and 54% enhancement of light output power for porous and cluster LED respectively at an injection current of 20 mA. Moreover, simulation result showed consistency with experimental result. The increased probability of light scattering at the nano-textured GaN-air interface is the major reason for increasing the light extraction efficiency.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.252-255
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• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.992-998
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• 2009

We investigated the influence of organic solvents on the droplet properties of 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene), which was used for semiconductor of organic thin film transistors (OTFTs) and deposited by ink jet printing. From the result of the investigation, the conditions of a suitable solvent is that boiling point should be above $200^{\circ}C$ to reduce coffee stain and the surface tension above 32 dyn/cm to decrease the droplet size. Consequently, we selected tetralin which have a high boiling point ($207^{\circ}C$) and high surface tension (34.3 dyn/cm) as the solvent for TIPS-pentacene, and applied it to OTFTs. In fabrication process the conventional bank process employing photolithography and etching process was replaced by ink jet printed bank process, resulting in simplifying the process. Especially, polyvinylphenol was used for the bank, and the high hydrophobicity could improve the confinement of TIPS molecules inside the bank, enhancing the performance over the conventional hydrophilic polyvinylalcohol bank. The mobility was $0.18\;cm^2/Vs$, current on/off ratio $2.09{\times}10^5$, subthreshold slope 0.42 V/dec, and off state current $0.049\;pA/{\mu}m$.